//************************************************************************************
//#Project  :AD18F06A
//#Version  :v1
//#DATE     :20230920
//-------------------------change list------------------------------------------------
//==========================================================================================
//--Version.----------------Content---------------------------------------------Who---DATA--
//==========================================================================================
//|-1-|- initial version                                                                                 -|-Minjw


#ifndef	__AD18F06A_H

#define	__AD18F06A_H



#define xc8 	1
#define picc18 	0


#ifdef xc8
#define _XTAL_FREQ 16000000
#pragma intrinsic(_delay)
extern __nonreentrant void _delay(unsigned long);
#define __delay_us(x) _delay((unsigned long)((x)*(_XTAL_FREQ/4000000.0)))
#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ/4000.0)))
#endif



// #ifdef picc18
// #define _XTAL_FREQ 16000000
// #pragma inline(_delay)
// extern void _delay(unsigned long);
// #define __delay_us(x) _delay((unsigned long)((x)*(_XTAL_FREQ/4000000.0)))
// #define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ/4000.0)))
// #endif



#define SLEEP_PWIDLE() SMCR = 0X01; SLEEP();NOP();NOP()
#define SLEEP_PWSAVE() SMCR = 0X03; SLEEP();NOP();NOP()
#define SLEEP_DEEPPWSAVE()  SMCR = 0X05; SLEEP();NOP();NOP()
#define SLEEP_PWOFF() SMCR = 0X07; SLEEP();NOP();NOP()


//-----------------------------MAP_DEFINE-------------------------------

#define IO_A 0
#define IO_B 1
#define IO_C 2
#define IO_D 3

#define PIN0 0
#define PIN1 1
#define PIN2 2
#define PIN3 3
#define PIN4 4
#define PIN5 5
#define PIN6 6
#define PIN7 7

#define MAP_PA0 (IO_A<<3)|PIN0
#define MAP_PA1 (IO_A<<3)|PIN1
#define MAP_PA2 (IO_A<<3)|PIN2
#define MAP_PA3 (IO_A<<3)|PIN3
#define MAP_PA4 (IO_A<<3)|PIN4
#define MAP_PA5 (IO_A<<3)|PIN5

#define MAP_PB0 (IO_B<<3)|PIN0
#define MAP_PB1 (IO_B<<3)|PIN1
#define MAP_PB2 (IO_B<<3)|PIN2
#define MAP_PB3 (IO_B<<3)|PIN3
#define MAP_PB4 (IO_B<<3)|PIN4
#define MAP_PB5 (IO_B<<3)|PIN5
#define MAP_PB6 (IO_B<<3)|PIN6
#define MAP_PB7 (IO_B<<3)|PIN7

#define MAP_PC0 (IO_C<<3)|PIN0
#define MAP_PC1 (IO_C<<3)|PIN1
#define MAP_PC2 (IO_C<<3)|PIN2
#define MAP_PC3 (IO_C<<3)|PIN3
#define MAP_PC4 (IO_C<<3)|PIN4
#define MAP_PC5 (IO_C<<3)|PIN5
#define MAP_PC6 (IO_C<<3)|PIN6
#define MAP_PC7 (IO_C<<3)|PIN7

#define MAP_PD0 (IO_D<<3)|PIN0
#define MAP_PD1 (IO_D<<3)|PIN1
#define MAP_PD2 (IO_D<<3)|PIN2
#define MAP_PD3 (IO_D<<3)|PIN3
#define MAP_PD4 (IO_D<<3)|PIN4
#define MAP_PD5 (IO_D<<3)|PIN5
#define MAP_PD6 (IO_D<<3)|PIN6
#define MAP_PD7 (IO_D<<3)|PIN7

//How to use
//example:
//
//   TX0_MAP = MAP_PA2;
//   RX0_MAP = MAP_PA3;

//
//-----------------------------------CONCFG------------------------------
/*
__CONFIG(1,_FINTOSC_DIV1_1L   & _LVREN_ON_1L       & _LVT20V_1L                                                                );
__CONFIG(2,_FLASH_CP7_OFF_2L  & _FLASH_CP6_OFF_2L  & _FLASH_CP5_OFF_2L   & _FLASH_CP4_OFF_2L   & _FLASH_CP3_OFF_2L
         & _FLASH_CP2_OFF_2L  & _FLASH_CP1_OFF_2L  & _FLASH_CP0_OFF_2L   & _CRYLEN_OFF_2L      & _CRYHEN_OFF_2L
  	     & _IDIS_OFF_2L       & _CKSUM_OFF_2L      & _CBP_OFF_2L         & _RESETE_OFF_2L      & _RSEL_LOW_2L     & _STV_ON_2L  );
__CONFIG(3, _DBG_OFF_3L & _PSUT_1_3L         & _FCPU_2T_3L        & _WDTEN_OFF_3L       & _TWDT_000_3L                                         );
__CONFIG(4,_OSCM_HIRC_16M_4L  &_ENVDDL_ON_4L       & _EEDIS_OFF_4L       & _FLDIS_OFF_4L    & _FCMEN_OFF_4L      & _IESO_OFF_4L    &       _DBGS_IOSEL_1_4L      );
*/


//STACK Register Define;
static volatile  unsigned char 				 TOSU				@0XFFF;
static volatile  unsigned char 				 TOSH				@0XFFE;
static volatile  unsigned char 				 TOSL		        @0XFFD;
static volatile  unsigned char  			 STKPTR		    	@0XFFC;

//PC Register Define;
static volatile  unsigned char  			 PCLATU				@0XFFB;
static volatile  unsigned char  			 PCLATH		   	    @0XFFA;
static volatile  unsigned char  			 PCL		     	@0XFF9;

//TBLPTR Register Define;
static volatile  unsigned char   			 TBLPTRU			@0XFF8;
static volatile  unsigned char   			 TBLPTRH			@0XFF7;
static volatile  unsigned char   			 TBLPTRL			@0XFF6;
static volatile  unsigned char 				 TABLAT				@0XFF5;

static volatile  unsigned char 				 PRODH				@0XFF4;
static volatile  unsigned char 				 PRODL		        @0XFF3;

static volatile  unsigned char               INTCON		    	@0XFF2;
static volatile  unsigned char 				 PCON   			@0XFF1;


//arrye one;
static volatile  unsigned char 				 INDF				@0XFEF;
static volatile  unsigned char 				 POSTINC0   	   	@0XFEE;
static volatile  unsigned char 				 POSTDEC0        	@0XFED;
static volatile  unsigned char 				 PREINC0        	@0XFEC;
static volatile  unsigned char 				 PLUSW0				@0XFEB;
static volatile  unsigned char 				 FSR0H				@0XFEA;
static volatile  unsigned char 				 FSR0L				@0XFE9;
static volatile  unsigned char 				 WREG				@0XFE8;

//arrye second;
static volatile  unsigned char 				 INDF1				@0XFE7;
static volatile  unsigned char 				 POSTINC1  		    @0XFE6;
static volatile  unsigned char 				 POSTDEC1      		@0XFE5;
static volatile  unsigned char 				 PREINC1        	@0XFE4;
static volatile  unsigned char 				 PLUSW1				@0XFE3;
static volatile  unsigned char 				 FSR1H				@0XFE2;
static volatile  unsigned char 				 FSR1L				@0XFE1;
static volatile  unsigned char 				 BSR			    @0XFE0;

//arrye third;
static volatile  unsigned char 				 INDF2				@0XFDF;
static volatile  unsigned char 				 POSTINC2 		   	@0XFDE;
static volatile  unsigned char				 POSTDEC2  		    @0XFDD;
static volatile  unsigned char				 PREINC2        	@0XFDC;
static volatile  unsigned char 				 PLUSW2				@0XFDB;
static volatile  unsigned char 				 FSR2H				@0XFDA;
static volatile  unsigned char				 FSR2L				@0XFD9;
static volatile  unsigned char             	 STATUS			        @0XFD8;
//------------------------------TMR0-----------------------------------------
static volatile  unsigned char 				 T0CON0				@0XFD7;
static volatile  unsigned char 				 PR0		    	@0XFD6;
static volatile  unsigned char 				 TMR0		    	@0XFD5;
static volatile  unsigned char 				 PWM0DUTY           @0XFD4;
static volatile  unsigned char 				 T0CON1 	    	@0XFD3;
 static volatile  unsigned char 		     RCON 				@0XFD2;
//-----------------------------TMR1----------------------------------------------
static volatile  unsigned char               TMR1H				@0XFD1;
static volatile  unsigned char 				 TMR1L		    	@0XFD0;
static volatile  unsigned char 				 T1CON0		        @0XFCF;
static volatile  unsigned char 				 T1CON1 			@0XFCE;
//-----------------------------TMR2----------------------------------------------
static volatile  unsigned char 				 TMR2L    		   	@0XFCD;
static volatile  unsigned char 				 TMR2H    		    @0XFCC;
static volatile  unsigned char  			 PR2L		    	@0XFCB;
static volatile  unsigned char  			 PR2H		        @0XFCA;
static volatile  unsigned char  			 T2CON  		    @0XFC9;
//-----------------------------CCP----------------------------------------------
static volatile  unsigned char  			 CCPR1H 	   		@0XFC8;
static volatile  unsigned char  			 CCPR1L 			@0XFC7;
static volatile  unsigned char  			 CCPR1LH			@0XFC6;
static volatile  unsigned char               PMS    		    @0XFC5;
static volatile  unsigned char  			 PXC    	        @0XFC4;
static volatile  unsigned char  			 DTC    	        @0XFC3;
static volatile  unsigned char  			 POLS       		@0XFC2;
static volatile  unsigned char    			 PME		    	@0XFC1;
static volatile  unsigned char    			 CCPCON1		   	@0XFC0;
static volatile  unsigned char    			 CCPCON0		    @0XFBF;
static volatile  unsigned char    			 PWM1CON0		    @0XFBE;
static volatile  unsigned char    			 PWM1CON1		    @0XFBD;
//-----------------------------TMR3------------------------------------------
static volatile  unsigned char  			 T3CON 	    	    @0XFBC;
static volatile  unsigned char 				 TMR3H 	    	    @0XFBB;
static volatile  unsigned char 				 TMR3L 			    @0XFBA;
static volatile  unsigned char  			 PR3H			    @0XFB9;
static volatile  unsigned char  			 PR3L	 		    @0XFB8;

//-----------------------------------PWM--------------------------------------
static volatile  unsigned char  			 PWM5H			   	@0XFB7;
static volatile  unsigned char				 PWM5L              @0XFB6;
static volatile  unsigned char				 PWM4H              @0XFB5;
static volatile  unsigned char				 PWM4L              @0XFB4;
static volatile  unsigned char				 PWM3H          	@0XFB3;
static volatile  unsigned char				 PWM3L          	@0XFB2;
static volatile  unsigned char				 PWM2H          	@0XFB1;
static volatile  unsigned char				 PWM2L             	@0XFB0;
static volatile  unsigned char 				 PWM2CON0	    	@0XFAF;
static volatile  unsigned char  			 PWM2CON1	    	@0XFAE;
//-----------------------------------INT--------------------------------------
static volatile  unsigned char  			 IPR1		    	@0XFAD;
static volatile  unsigned char               PIR1		    	@0XFAC;
static volatile  unsigned char  			 PIE1		    	@0XFAB;

static volatile  unsigned char  			 IPR2		    	@0XFAA;
static volatile  unsigned char  			 PIR2		        @0XFA9;
static volatile  unsigned char  			 PIE2	        	@0XFA8;

static volatile  unsigned char               IPR3		   	    @0XFA7;
static volatile  unsigned char  			 PIR3				@0XFA6;
static volatile  unsigned char               PIE3		    	@0XFA5;

static volatile  unsigned char               IPR4		   	    @0XFA4;
static volatile  unsigned char  			 PIR4				@0XFA3;
static volatile  unsigned char               PIE4		        @0XFA2;

static volatile  unsigned char  			 WDTCON 	       	@0XFA1;
static volatile  unsigned char  			 OSCTUNE			@0XFA0;

//----------------------------------GPIO----------------------------------

static volatile  unsigned char  			 ANASEL0		    @0XF9F;
static volatile  unsigned char  			 ANASEL1		    @0XF9E;
static volatile  unsigned char				 ANASEL2            @0XF9D;
static volatile  unsigned char				 ANASEL3            @0XF9C;

static volatile  unsigned char  			 SMTD		        @0XF9B;
static volatile  unsigned char  			 SMTC		    	@0XF9A;
static volatile  unsigned char  			 SMTB		    	@0XF99;
static volatile  unsigned char				 SMTA               @0XF98;

static volatile  unsigned char				 PDOD				@0XF97;
static volatile  unsigned char				 PCOD				@0XF96;
static volatile  unsigned char				 PBOD				@0XF95;
static volatile  unsigned char				 PAOD            	@0XF94;


static volatile  unsigned char				 TRISD				@0XF93;
static volatile  unsigned char				 TRISC				@0XF92;
static volatile  unsigned char				 TRISB				@0XF91;
static volatile  unsigned char				 TRISA				@0XF90;

static volatile  unsigned char				 PDPD            	@0XF8F;
static volatile  unsigned char				 PCPD            	@0XF8E;
static volatile  unsigned char				 PBPD				@0XF8D;
static volatile  unsigned char				 PAPD				@0XF8C;

static volatile  unsigned char				 PIND               @0XF8B;
static volatile  unsigned char				 PINC            	@0XF8A;
static volatile  unsigned char				 PINB				@0XF89;
static volatile  unsigned char				 PINA            	@0XF88;

static volatile  unsigned char				 PDPU            	@0XF87;
static volatile  unsigned char				 PCPU            	@0XF86;
static volatile  unsigned char				 PBPU            	@0XF85;
static volatile  unsigned char				 PAPU				@0XF84;

static volatile  unsigned char				 PORTD            	@0XF83;
static volatile  unsigned char				 PORTC            	@0XF82;
static volatile  unsigned char				 PORTB            	@0XF81;
static volatile  unsigned char				 PORTA				@0XF80;
//----------------------------CMP---------------------------------------
static volatile  unsigned char  			 CMP0CON0		    @0XF7F;
static volatile  unsigned char				 CMP0CON1           @0XF7E;
static volatile  unsigned char				 CMP1CON0			@0XF7D;
static volatile  unsigned char  			 CMP1CON1		    @0XF7C;
static volatile  unsigned char				 CMP2CON0          	@0XF7B;
static volatile  unsigned char				 CMP2CON1			@0XF7A;

//----------------------------DAC---------------------------------------
static volatile  unsigned char				 DAC1CON			@0XF77;
static volatile  unsigned char				 DAC0CON			@0XF76;
//----------------------------OP---------------------------------------
static volatile  unsigned char  			 OP0CON0		    @0XF75;
static volatile  unsigned char  			 OP0CON1		    @0XF74;
static volatile  unsigned char  			 OP0CON2		    @0XF73;
static volatile  unsigned char  			 OP0CON3		    @0XF72;
static volatile  unsigned char  			 OP0CON4		   	@0XF71;
//-----------------------------FVR---------------------------------------
static volatile  unsigned char				 FVRCON0		    @0XF70;
static volatile  unsigned char				 FVRCON1			@0XF6F;
//-----------------------------LCD---------------------------------------
static volatile  unsigned char				 LCDCON0			@0XF6E;
static volatile  unsigned char				 LCDCON1			@0XF6D;
static volatile  unsigned char				 COMEN		    	@0XF6C;
static volatile  unsigned char				 SEGEN0           	@0XF6B;
static volatile  unsigned char				 SEGEN1           	@0XF6A;
static volatile  unsigned char				 SEGEN2           	@0XF69;
//-----------------------------DIV---------------------------------------
static volatile  unsigned char				 DIVIDENDH         	@0XF68;
static volatile  unsigned char				 DIVIDENDL          @0XF67;
static volatile  unsigned char				 DIVISORH        	@0XF66;
static volatile  unsigned char				 DIVISORL           @0XF65;
static volatile  unsigned char				 QUOTIENTH          @0XF64;
static volatile  unsigned char				 QUOTIENTL          @0XF63;
static volatile  unsigned char				 REMAINDERH        	@0XF62;
static volatile  unsigned char				 REMAINDERL        	@0XF61;
static volatile  unsigned char				 DIVCON          	@0XF60;
//-----------------------------------ADC--------------------------------------
static volatile  unsigned char	             ADCMP0H  		    @0XF5F;
static volatile  unsigned char	             ADCMP1H           	@0XF5E;
static volatile  unsigned char	             ADCMP01L           @0XF5D;
static volatile  unsigned char	             ADRESH3           	@0XF5C;
static volatile  unsigned char	             ADRESL3           	@0XF5B;
static volatile  unsigned char	             ADRESH2           	@0XF5A;
static volatile  unsigned char	             ADRESL2           	@0XF59;
static volatile  unsigned char	             ADRESH1           	@0XF58;
static volatile  unsigned char	             ADRESL1           	@0XF57;
static volatile  unsigned char	             ADRESH0           	@0XF56;
static volatile  unsigned char	             ADRESL0           	@0XF55;
static volatile  unsigned char	             ADCON0  	       	@0XF54;
static volatile  unsigned char	             ADCON1            	@0XF53;
static volatile  unsigned char	             ADCON3    	       	@0XF51;
static volatile  unsigned char	             CMP3CON0    	    @0XF50;
static volatile  unsigned char	             CMP3CON1    	    @0XF4F;

//---------------CLK---------------------------------------------------
static volatile  unsigned char               CLKCFG1           	@0XF4E;
static volatile  unsigned char               CLKCFG2           	@0XF4D;


//----------------------------GPIO-------------------------------
static volatile  unsigned char               PAINTMASK        	@0XF4C;
static volatile  unsigned char               PBINTMASK	      	@0XF4B;
static volatile  unsigned char               PCINTMASK 	      	@0XF4A;
static volatile  unsigned char               PDINTMASK        	@0XF49;
//---------------EEPROM--------------
static volatile  unsigned char               EEDAT            	@0XF48;
static volatile  unsigned char               EEADR            	@0XF47;
static volatile  unsigned char               EECON1           	@0XF46;
static volatile  unsigned char               EECON2           	@0XF45;
//------------------FLASH------------------
static volatile  unsigned char               IAPRIG           	@0XF44;
static volatile  unsigned char               IAPCTRL          	@0XF43;
static volatile  unsigned char               IAPADDRH         	@0XF42;
static volatile  unsigned char               IAPADDRL         	@0XF41;
static volatile  unsigned char               IAPDATH          	@0XF40;
static volatile  unsigned char               IAPDATL          	@0XF3F;
static volatile  unsigned char               IAPWAIT          	@0XF3E;


//--------UART---------------------
static volatile  unsigned char               SPBRG    	      	@0XF2E;
static volatile  unsigned char               RCREG           	@0XF2D;
static volatile  unsigned char               TXREG           	@0XF2C;
static volatile  unsigned char               TXSTA   	      	@0XF2B;
static volatile  unsigned char               RCSTA          	@0XF2A;
static volatile  unsigned char               UARTCON         	@0XF29;
static volatile  unsigned char               SPBRG1    	      	@0XF28;
static volatile  unsigned char               RCREG1           	@0XF27;
static volatile  unsigned char               TXREG1           	@0XF26;
static volatile  unsigned char               TXSTA1   	      	@0XF25;
static volatile  unsigned char               RCSTA1           	@0XF24;
static volatile  unsigned char               UARTCON1         	@0XF23;

//--------I2C---------------------
static volatile  unsigned char               I2CACKDLY	      	@0XF22;
static volatile  unsigned char               I2CTX	      		@0XF21;
static volatile  unsigned char               I2CRC            	@0XF20;
static volatile  unsigned char               I2CADD0	      	@0XF1F;
static volatile  unsigned char               I2CADD1	      	@0XF1E;
static volatile  unsigned char               I2CADDMASK       	@0XF1D;
static volatile  unsigned char               I2CSTAT          	@0XF1C;
static volatile  unsigned char               I2CCON0  	      	@0XF1B;
static volatile  unsigned char               I2CCON1          	@0XF1A;
static volatile  unsigned char               I2CIE            	@0XF19;
static volatile  unsigned char               I2CIF   	      	@0XF18;
static volatile  unsigned char               I2CIP            	@0XF17;

//--------SPI---------------------
static volatile  unsigned char               SPCON            	@0XF16;
static volatile  unsigned char               SPSTA            	@0XF15;
static volatile  unsigned char               SPDAT            	@0XF14;
static volatile  unsigned char               EFTCON            	@0XF13;

static volatile  unsigned char               OSCCON           	@0XF12;
static volatile  unsigned char               SIGCON           	@0XF11;

static volatile  unsigned char               SMCR             	@0XF10;
static volatile  unsigned char               PDSINKCUR          @0XF0F;
static volatile  unsigned char               CURCON           	@0XF0E;

//--------MAP REGISTER---------------------
static volatile  unsigned char               TX0_MAP          	@0XEFF;
static volatile  unsigned char               RX0_MAP          	@0XEFE;
static volatile  unsigned char               TX1_MAP          	@0XEFD;
static volatile  unsigned char               RX1_MAP          	@0XEFC;
static volatile  unsigned char               SDA_MAP          	@0XEFB;
static volatile  unsigned char               SCL_MAP          	@0XEFA;
static volatile  unsigned char               PWM0_MAP         	@0XEF9;
static volatile  unsigned char               PWM00_MAP        	@0XEF8;
static volatile  unsigned char               PWM01_MAP        	@0XEF7;
static volatile  unsigned char               PWM10_MAP        	@0XEF6;
static volatile  unsigned char               PWM11_MAP        	@0XEF5;
static volatile  unsigned char               PWM20_MAP        	@0XEF4;
static volatile  unsigned char               PWM21_MAP        	@0XEF3;
static volatile  unsigned char               PWM2_MAP         	@0XEF2;
static volatile  unsigned char               PWM3_MAP         	@0XEF1;
static volatile  unsigned char               PWM4_MAP         	@0XEF0;
static volatile  unsigned char               PWM5_MAP         	@0XEEF;



static volatile  unsigned char               CMP0CON2          	@0XEEC;
static volatile  unsigned char               CMP1CON2          	@0XEEB;
static volatile  unsigned char               CMP3CON2          	@0XEEA;





//--------------------------------------------------------------------------
/* Definitions for STKPTR register */
static volatile  bit	STKFUL                            @ ((unsigned)&STKPTR*8)+7;
static volatile  bit	STKUNF                            @ ((unsigned)&STKPTR*8)+6;
static volatile  bit	SP4                               @ ((unsigned)&STKPTR*8)+4;
static volatile  bit	SP3                               @ ((unsigned)&STKPTR*8)+3;
static volatile  bit	SP2                               @ ((unsigned)&STKPTR*8)+2;
static volatile  bit	SP1                               @ ((unsigned)&STKPTR*8)+1;
static volatile  bit	SP0                               @ ((unsigned)&STKPTR*8)+0;
/* Definitions for PCON register */
static volatile  bit	IPEN                              @ ((unsigned)&PCON*8)+7;
static volatile  bit	PB0ST                             @ ((unsigned)&PCON*8)+6;
static volatile  bit	LVDM1                             @ ((unsigned)&PCON*8)+5;
static volatile  bit	LVDM0                             @ ((unsigned)&PCON*8)+4;
static volatile  bit	LVT3                              @ ((unsigned)&PCON*8)+3;
static volatile  bit	LVT2                              @ ((unsigned)&PCON*8)+2;
static volatile  bit	LVT1                              @ ((unsigned)&PCON*8)+1;
static volatile  bit	LVT0                              @ ((unsigned)&PCON*8)+0;
/* Definitions for STATUS register */
static volatile  bit	N     			                  @ ((unsigned)&STATUS*8)+4;
static volatile  bit	OV       		                  @ ((unsigned)&STATUS*8)+3;
static volatile  bit	Z   	         	              @ ((unsigned)&STATUS*8)+2;
static volatile  bit	D       		                  @ ((unsigned)&STATUS*8)+1;
static volatile  bit	C   			                  @ ((unsigned)&STATUS*8)+0;
/* Definitions for INTCON register */
static volatile   bit	PEIE		                      @ ((unsigned)&INTCON*8)+6;
static volatile   bit	GIEL			                  @ ((unsigned)&INTCON*8)+6;
static volatile   bit	GIE  			                  @ ((unsigned)&INTCON*8)+7;
static volatile   bit	GIEH   			                  @ ((unsigned)&INTCON*8)+7;
/* Definitions for RCON register */
static volatile  bit	IRFEN	        	              @ ((unsigned)&RCON*8)+7;
static volatile  bit	EMCEN					          @ ((unsigned)&RCON*8)+6;
static volatile  bit	RSTF1					          @ ((unsigned)&RCON*8)+5;
static volatile  bit	RSTF0				              @ ((unsigned)&RCON*8)+4;
static volatile  bit	TO				                  @ ((unsigned)&RCON*8)+3;
static volatile  bit	PD				                  @ ((unsigned)&RCON*8)+2;
static volatile  bit	POR				                  @ ((unsigned)&RCON*8)+1;
static volatile  bit	BOR				                  @ ((unsigned)&RCON*8)+0;

//-----------------------------------TIMER0-----------------------------------
/* Definitions for T0CON register */
static volatile  bit	T0OUT		                      @ ((unsigned)&T0CON0*8)+7;
static volatile  bit	T0CS2		                      @ ((unsigned)&T0CON0*8)+6;
static volatile  bit	T0CS1		                      @ ((unsigned)&T0CON0*8)+5;
static volatile  bit	T0CS0     	                      @ ((unsigned)&T0CON0*8)+4;
static volatile  bit	PSA		                          @ ((unsigned)&T0CON0*8)+3;
static volatile  bit	PS2		                          @ ((unsigned)&T0CON0*8)+2;
static volatile  bit	PS1		                          @ ((unsigned)&T0CON0*8)+1;
static volatile  bit	PS0		                          @ ((unsigned)&T0CON0*8)+0;
/* Definitions for T0CON1 register */
static volatile  bit	T1BUZEN                           @ ((unsigned)&T0CON1*8)+7;
static volatile  bit	T0DEGE		                      @ ((unsigned)&T0CON1*8)+6;
static volatile  bit	T0CH1		                      @ ((unsigned)&T0CON1*8)+5;
static volatile  bit	T0CH0		                      @ ((unsigned)&T0CON1*8)+4;
static volatile  bit	POLS0		                      @ ((unsigned)&T0CON1*8)+3;
static volatile  bit	PWM0EN		                      @ ((unsigned)&T0CON1*8)+2;
static volatile  bit	T0M1		                      @ ((unsigned)&T0CON1*8)+1;
static volatile  bit	T0M0		                      @ ((unsigned)&T0CON1*8)+0;

/* Definitions for T1CON0 register */
static volatile  bit	T1CK2		                      @ ((unsigned)&T1CON0*8)+7;
static volatile  bit	T1CK1		                      @ ((unsigned)&T1CON0*8)+6;
static volatile  bit	T1CK0		                      @ ((unsigned)&T1CON0*8)+5;
static volatile  bit	T1CKPS1    	                      @ ((unsigned)&T1CON0*8)+4;
static volatile  bit	T1CKPS0 	                      @ ((unsigned)&T1CON0*8)+3;
static volatile  bit	T1SYNC		                      @ ((unsigned)&T1CON0*8)+2;
static volatile  bit	TMR1CS0		                      @ ((unsigned)&T1CON0*8)+1;
static volatile  bit	TMR1ON		                      @ ((unsigned)&T1CON0*8)+0;
/* Definitions for T1CON1 register */
static volatile  bit	INT2EDGE	                      @ ((unsigned)&T1CON1*8)+7;
static volatile  bit	INT1EDGE	                      @ ((unsigned)&T1CON1*8)+6;
static volatile  bit	INT0EDGE		                  @ ((unsigned)&T1CON1*8)+5;
static volatile  bit	T1EDGE    	                      @ ((unsigned)&T1CON1*8)+4;
static volatile  bit	T1CH1		                      @ ((unsigned)&T1CON1*8)+3;
static volatile  bit	T1CH0		                      @ ((unsigned)&T1CON1*8)+2;
static volatile  bit	T1M1		                      @ ((unsigned)&T1CON1*8)+1;
static volatile  bit	T1M0		                      @ ((unsigned)&T1CON1*8)+0;
/* Definitions for T2CON register */
static volatile  bit	PWM2CAEN 	                      @ ((unsigned)&T2CON*8)+7;
static volatile  bit	T2OUTPS3	                      @ ((unsigned)&T2CON*8)+6;
static volatile  bit	T2OUTPS2	                      @ ((unsigned)&T2CON*8)+5;
static volatile  bit	T2OUTPS1	                      @ ((unsigned)&T2CON*8)+4;
static volatile  bit	T2OUTPS0	                      @ ((unsigned)&T2CON*8)+3;
static volatile  bit	TMR2ON		                      @ ((unsigned)&T2CON*8)+2;
static volatile  bit	T2CKPS1		                      @ ((unsigned)&T2CON*8)+1;
static volatile  bit	T2CKPS0		                      @ ((unsigned)&T2CON*8)+0;

/* Definitions for PMS register */
static volatile bit    DMISTK2                            @ ((unsigned)&PMS*8)+7;
static volatile bit    PWMH                               @ ((unsigned)&PMS*8)+6;
static volatile bit    PMS21                              @ ((unsigned)&PMS*8)+5;
static volatile bit    PMS20                              @ ((unsigned)&PMS*8)+4;
static volatile bit    PMS11                              @ ((unsigned)&PMS*8)+3;
static volatile bit    PMS10                              @ ((unsigned)&PMS*8)+2;
static volatile bit    PMS01                              @ ((unsigned)&PMS*8)+1;
static volatile bit    PMS00                              @ ((unsigned)&PMS*8)+0;
/* Definitions for PXC register */
static volatile bit    T3PWMEN                            @ ((unsigned)&PXC*8)+7;
static volatile bit    T3PWMMODE                          @ ((unsigned)&PXC*8)+6;
static volatile bit    PXC21                              @ ((unsigned)&PXC*8)+5;
static volatile bit    PXC20                              @ ((unsigned)&PXC*8)+4;
static volatile bit    PXC11                              @ ((unsigned)&PXC*8)+3;
static volatile bit    PXC10                              @ ((unsigned)&PXC*8)+2;
static volatile bit    PXC01                              @ ((unsigned)&PXC*8)+1;
static volatile bit    PXC00                              @ ((unsigned)&PXC*8)+0;
/* Definitions for DTC register */
static volatile bit    DTCKS1                             @ ((unsigned)&DTC*8)+7;
static volatile bit    DTCKS0                             @ ((unsigned)&DTC*8)+6;
static volatile bit    DTEN                               @ ((unsigned)&DTC*8)+5;
static volatile bit    DTD4                               @ ((unsigned)&DTC*8)+4;
static volatile bit    DTD3                               @ ((unsigned)&DTC*8)+3;
static volatile bit    DTD2                               @ ((unsigned)&DTC*8)+2;
static volatile bit    DTD1                               @ ((unsigned)&DTC*8)+1;
static volatile bit    DTD0                               @ ((unsigned)&DTC*8)+0;
/* Definitions for POLS register */

static volatile bit    PT2MODE                            @ ((unsigned)&POLS*8)+6;
static volatile bit    POLS21                             @ ((unsigned)&POLS*8)+5;
static volatile bit    POLS20                             @ ((unsigned)&POLS*8)+4;
static volatile bit    POLS11                             @ ((unsigned)&POLS*8)+3;
static volatile bit    POLS10                             @ ((unsigned)&POLS*8)+2;
static volatile bit    POLS01                             @ ((unsigned)&POLS*8)+1;
static volatile bit    POLS00                             @ ((unsigned)&POLS*8)+0;
/* Definitions for PME register */
static volatile bit    PT1MODE                            @ ((unsigned)&PME*8)+7;
static volatile bit    PT0MODE                            @ ((unsigned)&PME*8)+6;
static volatile bit    PWM2EN1                            @ ((unsigned)&PME*8)+5;
static volatile bit    PWM2EN0                            @ ((unsigned)&PME*8)+4;
static volatile bit    PWM1EN1                            @ ((unsigned)&PME*8)+3;
static volatile bit    PWM1EN0                            @ ((unsigned)&PME*8)+2;
static volatile bit    PWM0EN1                            @ ((unsigned)&PME*8)+1;
static volatile bit    PWM0EN0                            @ ((unsigned)&PME*8)+0;

/* Definitions for CCPR1LH  register */
static volatile bit    T2CAPEN                            @ ((unsigned)&CCPR1LH*8)+7;
static volatile bit    CAP_PHASE2                         @ ((unsigned)&CCPR1LH*8)+6;
static volatile bit    CAP_PHASE1                         @ ((unsigned)&CCPR1LH*8)+5;
static volatile bit    CAP_PHASE0                         @ ((unsigned)&CCPR1LH*8)+4;

/* Definitions for CCPCON1 register */
static volatile bit    CCP2CH3                            @ ((unsigned)&CCPCON1*8)+7;
static volatile bit    CCP2CH2                            @ ((unsigned)&CCPCON1*8)+6;
static volatile bit    CCP2CH1                            @ ((unsigned)&CCPCON1*8)+5;
static volatile bit    CCP2CH0                            @ ((unsigned)&CCPCON1*8)+4;
static volatile bit    CCP1CH3                            @ ((unsigned)&CCPCON1*8)+3;
static volatile bit    CCP1CH2                            @ ((unsigned)&CCPCON1*8)+2;
static volatile bit    CCP1CH1                            @ ((unsigned)&CCPCON1*8)+1;
static volatile bit    CCP1CH0                            @ ((unsigned)&CCPCON1*8)+0;

/* Definitions for CCPCON0   register */
static volatile bit    CCP0CH3                            @ ((unsigned)&CCPCON0*8)+7;
static volatile bit    CCP0CH2                            @ ((unsigned)&CCPCON0*8)+6;
static volatile bit    CCP0CH1                            @ ((unsigned)&CCPCON0*8)+5;
static volatile bit    CCP0CH0                            @ ((unsigned)&CCPCON0*8)+4;
static volatile bit    CCP1M3                             @ ((unsigned)&CCPCON0*8)+3;
static volatile bit    CCP1M2                             @ ((unsigned)&CCPCON0*8)+2;
static volatile bit    CCP1M1                             @ ((unsigned)&CCPCON0*8)+1;
static volatile bit    CCP1M0                             @ ((unsigned)&CCPCON0*8)+0;
/* Definitions for PWM1CON0 register */
static volatile bit     OPFLT                             @ ((unsigned)&PWM1CON0*8)+7;
static volatile bit     EFTFLT                            @ ((unsigned)&PWM1CON0*8)+6;
static volatile bit     ASTART                            @ ((unsigned)&PWM1CON0*8)+5;
static volatile bit     ACLOSE                            @ ((unsigned)&PWM1CON0*8)+4;
static volatile bit     IOFLT                             @ ((unsigned)&PWM1CON0*8)+3;
static volatile bit     PWMADPOS1                         @ ((unsigned)&PWM1CON0*8)+2;
static volatile bit     PWMADPOS0                         @ ((unsigned)&PWM1CON0*8)+1;
static volatile bit     PWMADEN                           @ ((unsigned)&PWM1CON0*8)+0;
/* Definitions for T3CON register */
static volatile  bit	PWM3CAEN 	                      @ ((unsigned)&T3CON*8)+7;
static volatile  bit	T3OUTPS3	                      @ ((unsigned)&T3CON*8)+6;
static volatile  bit	T3OUTPS2	                      @ ((unsigned)&T3CON*8)+5;
static volatile  bit	T3OUTPS1	                      @ ((unsigned)&T3CON*8)+4;
static volatile  bit	T3OUTPS0	                      @ ((unsigned)&T3CON*8)+3;
static volatile  bit	TMR3ON		                      @ ((unsigned)&T3CON*8)+2;
static volatile  bit	T3CKPS1		                      @ ((unsigned)&T3CON*8)+1;
static volatile  bit	T3CKPS0		                      @ ((unsigned)&T3CON*8)+0;
/* Definitions for PWM2CON0 register */
static volatile bit     PWM5OEN                           @ ((unsigned)&PWM2CON0*8)+7;
static volatile bit     PWM4OEN                           @ ((unsigned)&PWM2CON0*8)+6;
static volatile bit     PWM3OEN                           @ ((unsigned)&PWM2CON0*8)+5;
static volatile bit     PWM2OEN                           @ ((unsigned)&PWM2CON0*8)+4;
static volatile bit     PWM5EN                            @ ((unsigned)&PWM2CON0*8)+3;
static volatile bit     PWM4EN                            @ ((unsigned)&PWM2CON0*8)+2;
static volatile bit     PWM3EN                            @ ((unsigned)&PWM2CON0*8)+1;
static volatile bit     PWM2EN                            @ ((unsigned)&PWM2CON0*8)+0;
/* Definitions for PWM2CON1 register */
static volatile bit     CMP3FLT                           @ ((unsigned)&PWM2CON1*8)+7;
static volatile bit     CMP2FLT                           @ ((unsigned)&PWM2CON1*8)+6;
static volatile bit     CMP1FLT                           @ ((unsigned)&PWM2CON1*8)+5;
static volatile bit     CMP0FLT                           @ ((unsigned)&PWM2CON1*8)+4;
static volatile bit     POLS5                             @ ((unsigned)&PWM2CON1*8)+3;
static volatile bit     POLS4                             @ ((unsigned)&PWM2CON1*8)+2;
static volatile bit     POLS3                             @ ((unsigned)&PWM2CON1*8)+1;
static volatile bit     POLS2                             @ ((unsigned)&PWM2CON1*8)+0;

/* Definitions for IPR1 register */
static volatile bit     SPIIP	                          @ ((unsigned)&IPR1*8)+7;
static volatile bit     EEIP	                          @ ((unsigned)&IPR1*8)+6;
static volatile bit     OSFIP	                          @ ((unsigned)&IPR1*8)+5;
static volatile bit     CCPIP                             @ ((unsigned)&IPR1*8)+4;
static volatile bit     TMR3IP                            @ ((unsigned)&IPR1*8)+3;
static volatile bit     TMR2IP                            @ ((unsigned)&IPR1*8)+2;
static volatile bit     TMR1IP                            @ ((unsigned)&IPR1*8)+1;
static volatile bit     TMR0IP                            @ ((unsigned)&IPR1*8)+0;

/* Definitions for PIR1 register */
static volatile bit     SPIIF	                          @ ((unsigned)&PIR1*8)+7;
static volatile bit     EEIF	                          @ ((unsigned)&PIR1*8)+6;
static volatile bit     OSFIF	                          @ ((unsigned)&PIR1*8)+5;
static volatile bit     CCPIF                             @ ((unsigned)&PIR1*8)+4;
static volatile bit     TMR3IF                            @ ((unsigned)&PIR1*8)+3;
static volatile bit     TMR2IF                            @ ((unsigned)&PIR1*8)+2;
static volatile bit     TMR1IF                            @ ((unsigned)&PIR1*8)+1;
static volatile bit     TMR0IF                            @ ((unsigned)&PIR1*8)+0;
/* Definitions for PIE1 register */

static volatile bit     SPIIE                              @ ((unsigned)&PIE1*8)+7;
static volatile bit     EEIE		                      @ ((unsigned)&PIE1*8)+6;
static volatile bit     OSFIE                             @ ((unsigned)&PIE1*8)+5;
static volatile bit     CCPIE                             @ ((unsigned)&PIE1*8)+4;
static volatile bit     TMR3IE                            @ ((unsigned)&PIE1*8)+3;
static volatile bit     TMR2IE                            @ ((unsigned)&PIE1*8)+2;
static volatile bit     TMR1IE                            @ ((unsigned)&PIE1*8)+1;
static volatile bit     TMR0IE                            @ ((unsigned)&PIE1*8)+0;

/* Definitions for IPR2 register */
static volatile bit     ADCMP1IP                          @ ((unsigned)&IPR2*8)+6;
static volatile bit     ADCMP0IP                          @ ((unsigned)&IPR2*8)+5;
static volatile bit     ADIP                              @ ((unsigned)&IPR2*8)+4;
static volatile bit     RCIP                              @ ((unsigned)&IPR2*8)+3;
static volatile bit     TXIP                              @ ((unsigned)&IPR2*8)+2;
static volatile bit     RC1IP                             @ ((unsigned)&IPR2*8)+1;
static volatile bit     TX1IP                             @ ((unsigned)&IPR2*8)+0;

/* Definitions for PIR2 register */

static volatile bit     ADCMP1IF                          @ ((unsigned)&PIR2*8)+6;
static volatile bit     ADCMP0IF                          @ ((unsigned)&PIR2*8)+5;
static volatile bit     ADIF                              @ ((unsigned)&PIR2*8)+4;
static volatile bit     RCIF                              @ ((unsigned)&PIR2*8)+3;
static volatile bit     TXIF                              @ ((unsigned)&PIR2*8)+2;
static volatile bit     RC1IF                             @ ((unsigned)&PIR2*8)+1;
static volatile bit     TX1IF                             @ ((unsigned)&PIR2*8)+0;
/* Definitions for PIE2 register */

static volatile bit     ADCMP1IE                          @ ((unsigned)&PIE2*8)+6;
static volatile bit     ADCMP0IE                          @ ((unsigned)&PIE2*8)+5;
static volatile bit     ADIE                              @ ((unsigned)&PIE2*8)+4;
static volatile bit     RCIE                              @ ((unsigned)&PIE2*8)+3;
static volatile bit     TXIE                              @ ((unsigned)&PIE2*8)+2;
static volatile bit     RC1IE                             @ ((unsigned)&PIE2*8)+1;
static volatile bit     TX1IE                             @ ((unsigned)&PIE2*8)+0;

/* Definitions for IPR3 register */

static volatile bit     PDIP                              @ ((unsigned)&IPR3*8)+7;
static volatile bit     PCIP                              @ ((unsigned)&IPR3*8)+6;
static volatile bit     PBIP                              @ ((unsigned)&IPR3*8)+5;
static volatile bit     PAIP                              @ ((unsigned)&IPR3*8)+4;
static volatile bit     INT2IP                            @ ((unsigned)&IPR3*8)+3;
static volatile bit     INT1IP                            @ ((unsigned)&IPR3*8)+2;
static volatile bit     INT0IP                            @ ((unsigned)&IPR3*8)+1;
static volatile bit     LVDIP                             @ ((unsigned)&IPR3*8)+0;

/* Definitions for PIR3 register */
static volatile bit     PDIF                              @ ((unsigned)&PIR3*8)+7;
static volatile bit     PCIF                              @ ((unsigned)&PIR3*8)+6;
static volatile bit     PBIF                              @ ((unsigned)&PIR3*8)+5;
static volatile bit     PAIF                              @ ((unsigned)&PIR3*8)+4;
static volatile bit     INT2IF                            @ ((unsigned)&PIR3*8)+3;
static volatile bit     INT1IF                            @ ((unsigned)&PIR3*8)+2;
static volatile bit     INT0IF                            @ ((unsigned)&PIR3*8)+1;
static volatile bit     LVDIF                             @ ((unsigned)&PIR3*8)+0;

/* Definitions for PIE3 register */

static volatile bit     PDIE                              @ ((unsigned)&PIE3*8)+7;
static volatile bit     PCIE                              @ ((unsigned)&PIE3*8)+6;
static volatile bit     PBIE                              @ ((unsigned)&PIE3*8)+5;
static volatile bit     PAIE                              @ ((unsigned)&PIE3*8)+4;
static volatile bit     INT2IE                            @ ((unsigned)&PIE3*8)+3;
static volatile bit     INT1IE                            @ ((unsigned)&PIE3*8)+2;
static volatile bit     INT0IE                            @ ((unsigned)&PIE3*8)+1;
static volatile bit     LVDIE                             @ ((unsigned)&PIE3*8)+0;

/* Definitions for IPR4 register */

static volatile bit     OP0IP                             @ ((unsigned)&IPR4*8)+6;
static volatile bit     CMP3IP                            @ ((unsigned)&IPR4*8)+5;
static volatile bit     CMP2IP                            @ ((unsigned)&IPR4*8)+4;
static volatile bit     CMP1IP                            @ ((unsigned)&IPR4*8)+3;
static volatile bit     CMP0IP                            @ ((unsigned)&IPR4*8)+2;


/* Definitions for PIR4 register */

static volatile bit     OP0IF                             @ ((unsigned)&PIR4*8)+6;
static volatile bit     CMP3IF                            @ ((unsigned)&PIR4*8)+5;
static volatile bit     CMP2IF                            @ ((unsigned)&PIR4*8)+4;
static volatile bit     CMP1IF                            @ ((unsigned)&PIR4*8)+3;
static volatile bit     CMP0IF                            @ ((unsigned)&PIR4*8)+2;


/* Definitions for PIE4 register */

static volatile bit     OP0IE                             @ ((unsigned)&PIE4*8)+6;
static volatile bit     CMP3IE                            @ ((unsigned)&PIE4*8)+5;
static volatile bit     CMP2IE                            @ ((unsigned)&PIE4*8)+4;
static volatile bit     CMP1IE                            @ ((unsigned)&PIE4*8)+3;
static volatile bit     CMP0IE                            @ ((unsigned)&PIE4*8)+2;

/* Definitions for WDTCON register */
static volatile bit    PREDIV2                            @ ((unsigned)&WDTCON*8)+3;
static volatile bit    PREDIV1                            @ ((unsigned)&WDTCON*8)+2;
static volatile bit    PREDIV0                            @ ((unsigned)&WDTCON*8)+1;
static volatile bit    SWDTEN                             @ ((unsigned)&WDTCON*8)+0;

/* Definitions for OSCTUNE register */
static volatile bit     OSCTUNE_EN                        @ ((unsigned)&OSCTUNE*8)+7;
static volatile bit     OSCTUNE6                          @ ((unsigned)&OSCTUNE*8)+6;
static volatile bit     OSCTUNE5                          @ ((unsigned)&OSCTUNE*8)+5;
static volatile bit     OSCTUNE4                          @ ((unsigned)&OSCTUNE*8)+4;
static volatile bit     OSCTUNE3                          @ ((unsigned)&OSCTUNE*8)+3;
static volatile bit     OSCTUNE2                          @ ((unsigned)&OSCTUNE*8)+2;
static volatile bit     OSCTUNE1                          @ ((unsigned)&OSCTUNE*8)+1;
static volatile bit     OSCTUNE0                          @ ((unsigned)&OSCTUNE*8)+0;
//---------------------------------------------GPIO--------------------------------------
/* Definitions for ANASEL0 register */
static volatile  bit	PA5AEN	                          @ ((unsigned)&ANASEL0*8)+5;
static volatile  bit	PA4AEN	                          @ ((unsigned)&ANASEL0*8)+4;
static volatile  bit	PA3AEN	                          @ ((unsigned)&ANASEL0*8)+3;
static volatile  bit	PA2AEN	                          @ ((unsigned)&ANASEL0*8)+2;
static volatile  bit	PA1AEN 	                          @ ((unsigned)&ANASEL0*8)+1;
static volatile  bit	PA0AEN	                          @ ((unsigned)&ANASEL0*8)+0;
/* Definitions for ANASEL1 register */
static volatile  bit	PB7AEN	                          @ ((unsigned)&ANASEL1*8)+7;
static volatile  bit	PB6AEN	                          @ ((unsigned)&ANASEL1*8)+6;
static volatile  bit	PB5AEN	                          @ ((unsigned)&ANASEL1*8)+5;
static volatile  bit	PB4AEN	                          @ ((unsigned)&ANASEL1*8)+4;
static volatile  bit	PB3AEN	                          @ ((unsigned)&ANASEL1*8)+3;
static volatile  bit	PB2AEN	                          @ ((unsigned)&ANASEL1*8)+2;
static volatile  bit	PB1AEN 	                          @ ((unsigned)&ANASEL1*8)+1;
static volatile  bit	PB0AEN	                          @ ((unsigned)&ANASEL1*8)+0;
/* Definitions for ANASEL2 register */
static volatile  bit	PC7AEN	                          @ ((unsigned)&ANASEL2*8)+7;
static volatile  bit	PC6AEN	                          @ ((unsigned)&ANASEL2*8)+6;
static volatile  bit	PC5AEN	                          @ ((unsigned)&ANASEL2*8)+5;
static volatile  bit	PC4AEN	                          @ ((unsigned)&ANASEL2*8)+4;
static volatile  bit	PC3AEN	                          @ ((unsigned)&ANASEL2*8)+3;
static volatile  bit	PC2AEN	                          @ ((unsigned)&ANASEL2*8)+2;
static volatile  bit	PC1AEN 	                          @ ((unsigned)&ANASEL2*8)+1;
static volatile  bit	PC0AEN	                          @ ((unsigned)&ANASEL2*8)+0;
/* Definitions for ANASEL3 register */
static volatile  bit	PD7AEN	                          @ ((unsigned)&ANASEL3*8)+7;
static volatile  bit	PD6AEN	                          @ ((unsigned)&ANASEL3*8)+6;
static volatile  bit	PD5AEN	                          @ ((unsigned)&ANASEL3*8)+5;
static volatile  bit	PD4AEN	                          @ ((unsigned)&ANASEL3*8)+4;
static volatile  bit	PD3AEN	                          @ ((unsigned)&ANASEL3*8)+3;
static volatile  bit	PD2AEN	                          @ ((unsigned)&ANASEL3*8)+2;
static volatile  bit	PD1AEN 	                          @ ((unsigned)&ANASEL3*8)+1;
static volatile  bit	PD0AEN	                          @ ((unsigned)&ANASEL3*8)+0;

/* Definitions for SMTA register */
static volatile  bit	SMTA5	                          @ ((unsigned)&SMTA*8)+5;
static volatile  bit	SMTA4	                          @ ((unsigned)&SMTA*8)+4;
static volatile  bit	SMTA3	                          @ ((unsigned)&SMTA*8)+3;
static volatile  bit	SMTA2	                          @ ((unsigned)&SMTA*8)+2;
static volatile  bit	SMTA1 	                          @ ((unsigned)&SMTA*8)+1;
static volatile  bit	SMTA0	                          @ ((unsigned)&SMTA*8)+0;
/* Definitions for SMTB register */
static volatile  bit	SMTB7	                          @ ((unsigned)&SMTB*8)+7;
static volatile  bit	SMTB6	                          @ ((unsigned)&SMTB*8)+6;
static volatile  bit	SMTB5	                          @ ((unsigned)&SMTB*8)+5;
static volatile  bit	SMTB4	                          @ ((unsigned)&SMTB*8)+4;
static volatile  bit	SMTB3	                          @ ((unsigned)&SMTB*8)+3;
static volatile  bit	SMTB2	                          @ ((unsigned)&SMTB*8)+2;
static volatile  bit	SMTB1 	                          @ ((unsigned)&SMTB*8)+1;
static volatile  bit	SMTB0	                          @ ((unsigned)&SMTB*8)+0;
/* Definitions for SMTC register */
static volatile  bit	SMTC7	                          @ ((unsigned)&SMTC*8)+7;
static volatile  bit	SMTC6	                          @ ((unsigned)&SMTC*8)+6;
static volatile  bit	SMTC5	                          @ ((unsigned)&SMTC*8)+5;
static volatile  bit	SMTC4	                          @ ((unsigned)&SMTC*8)+4;
static volatile  bit	SMTC3	                          @ ((unsigned)&SMTC*8)+3;
static volatile  bit	SMTC2	                          @ ((unsigned)&SMTC*8)+2;
static volatile  bit	SMTC1 	                          @ ((unsigned)&SMTC*8)+1;
static volatile  bit	SMTC0	                          @ ((unsigned)&SMTC*8)+0;
/* Definitions for SMTD register */
static volatile  bit	SMTD7	                          @ ((unsigned)&SMTD*8)+7;
static volatile  bit	SMTD6	                          @ ((unsigned)&SMTD*8)+6;
static volatile  bit	SMTD5	                          @ ((unsigned)&SMTD*8)+5;
static volatile  bit	SMTD4	                          @ ((unsigned)&SMTD*8)+4;
static volatile  bit	SMTD3	                          @ ((unsigned)&SMTD*8)+3;
static volatile  bit	SMTD2	                          @ ((unsigned)&SMTD*8)+2;
static volatile  bit	SMTD1 	                          @ ((unsigned)&SMTD*8)+1;
static volatile  bit	SMTD0	                          @ ((unsigned)&SMTD*8)+0;


/* Definitions for PDOD register */
static volatile  bit	PD7OD		                      @ ((unsigned)&PDOD*8)+7;
static volatile  bit	PD6OD		                      @ ((unsigned)&PDOD*8)+6;
static volatile  bit	PD5OD		                      @ ((unsigned)&PDOD*8)+5;
static volatile  bit	PD4OD		                      @ ((unsigned)&PDOD*8)+4;
static volatile  bit	PD3OD		                      @ ((unsigned)&PDOD*8)+3;
static volatile  bit	PD2OD		                      @ ((unsigned)&PDOD*8)+2;
static volatile  bit	PD1OD		                      @ ((unsigned)&PDOD*8)+1;
static volatile  bit	PD0OD		                      @ ((unsigned)&PDOD*8)+0;
/* Definitions for PCOD register */
static volatile  bit	PC7OD		                      @ ((unsigned)&PCOD*8)+7;
static volatile  bit	PC6OD		                      @ ((unsigned)&PCOD*8)+6;
static volatile  bit	PC5OD		                      @ ((unsigned)&PCOD*8)+5;
static volatile  bit	PC4OD		                      @ ((unsigned)&PCOD*8)+4;
static volatile  bit	PC3OD		                      @ ((unsigned)&PCOD*8)+3;
static volatile  bit	PC2OD		                      @ ((unsigned)&PCOD*8)+2;
static volatile  bit	PC1OD		                      @ ((unsigned)&PCOD*8)+1;
static volatile  bit	PC0OD		                      @ ((unsigned)&PCOD*8)+0;

/* Definitions for PBOD register */
static volatile  bit	PB7OD		                      @ ((unsigned)&PBOD*8)+7;
static volatile  bit	PB6OD		                      @ ((unsigned)&PBOD*8)+6;
static volatile  bit	PB5OD		                      @ ((unsigned)&PBOD*8)+5;
static volatile  bit	PB4OD		                      @ ((unsigned)&PBOD*8)+4;
static volatile  bit	PB3OD		                      @ ((unsigned)&PBOD*8)+3;
static volatile  bit	PB2OD		                      @ ((unsigned)&PBOD*8)+2;
static volatile  bit	PB1OD		                      @ ((unsigned)&PBOD*8)+1;
static volatile  bit	PB0OD		                      @ ((unsigned)&PBOD*8)+0;
/* Definitions for PAOD register */
static volatile  bit	PA5OD		                      @ ((unsigned)&PAOD*8)+5;
static volatile  bit	PA4OD		                      @ ((unsigned)&PAOD*8)+4;
static volatile  bit	PA3OD		                      @ ((unsigned)&PAOD*8)+3;
static volatile  bit	PA2OD		                      @ ((unsigned)&PAOD*8)+2;
static volatile  bit	PA1OD		                      @ ((unsigned)&PAOD*8)+1;
static volatile  bit	PA0OD		                      @ ((unsigned)&PAOD*8)+0;
/* Definitions for TRISD register */
static volatile  bit	TRISD7		                      @ ((unsigned)&TRISD*8)+7;
static volatile  bit	TRISD6		                      @ ((unsigned)&TRISD*8)+6;
static volatile  bit	TRISD5		                      @ ((unsigned)&TRISD*8)+5;
static volatile  bit	TRISD4		                      @ ((unsigned)&TRISD*8)+4;
static volatile  bit	TRISD3		                      @ ((unsigned)&TRISD*8)+3;
static volatile  bit	TRISD2		                      @ ((unsigned)&TRISD*8)+2;
static volatile  bit	TRISD1		                      @ ((unsigned)&TRISD*8)+1;
static volatile  bit	TRISD0		                      @ ((unsigned)&TRISD*8)+0;
/* Definitions for TRISC register */
static volatile  bit	TRISC7		                      @ ((unsigned)&TRISC*8)+7;
static volatile  bit	TRISC6		                      @ ((unsigned)&TRISC*8)+6;
static volatile  bit	TRISC5		                      @ ((unsigned)&TRISC*8)+5;
static volatile  bit	TRISC4		                      @ ((unsigned)&TRISC*8)+4;
static volatile  bit	TRISC3		                      @ ((unsigned)&TRISC*8)+3;
static volatile  bit	TRISC2		                      @ ((unsigned)&TRISC*8)+2;
static volatile  bit	TRISC1		                      @ ((unsigned)&TRISC*8)+1;
static volatile  bit	TRISC0		                      @ ((unsigned)&TRISC*8)+0;
/* Definitions for TRISB register */
static volatile  bit	TRISB7		                      @ ((unsigned)&TRISB*8)+7;
static volatile  bit	TRISB6		                      @ ((unsigned)&TRISB*8)+6;
static volatile  bit	TRISB5		                      @ ((unsigned)&TRISB*8)+5;
static volatile  bit	TRISB4		                      @ ((unsigned)&TRISB*8)+4;
static volatile  bit	TRISB3		                      @ ((unsigned)&TRISB*8)+3;
static volatile  bit	TRISB2		                      @ ((unsigned)&TRISB*8)+2;
static volatile  bit	TRISB1		                      @ ((unsigned)&TRISB*8)+1;
static volatile  bit	TRISB0		                      @ ((unsigned)&TRISB*8)+0;
/* Definitions for TRISA register */
static volatile  bit	TRISA5		                      @ ((unsigned)&TRISA*8)+5;
static volatile  bit	TRISA4		                      @ ((unsigned)&TRISA*8)+4;
static volatile  bit	TRISA3		                      @ ((unsigned)&TRISA*8)+3;
static volatile  bit	TRISA2		                      @ ((unsigned)&TRISA*8)+2;
static volatile  bit	TRISA1		                      @ ((unsigned)&TRISA*8)+1;
static volatile  bit	TRISA0		                      @ ((unsigned)&TRISA*8)+0;
/* Definitions for PDPD register */
static volatile  bit	PD7PD		                      @ ((unsigned)&PDPD*8)+7;
static volatile  bit	PD6PD		                      @ ((unsigned)&PDPD*8)+6;
static volatile  bit	PD5PD		                      @ ((unsigned)&PDPD*8)+5;
static volatile  bit	PD4PD		                      @ ((unsigned)&PDPD*8)+4;
static volatile  bit	PD3PD		                      @ ((unsigned)&PDPD*8)+3;
static volatile  bit	PD2PD		                      @ ((unsigned)&PDPD*8)+2;
static volatile  bit	PD1PD		                      @ ((unsigned)&PDPD*8)+1;
static volatile  bit	PD0PD		                      @ ((unsigned)&PDPD*8)+0;
/* Definitions for PCPD register */
static volatile  bit	PC7PD		                      @ ((unsigned)&PCPD*8)+7;
static volatile  bit	PC6PD		                      @ ((unsigned)&PCPD*8)+6;
static volatile  bit	PC5PD		                      @ ((unsigned)&PCPD*8)+5;
static volatile  bit	PC4PD		                      @ ((unsigned)&PCPD*8)+4;
static volatile  bit	PC3PD		                      @ ((unsigned)&PCPD*8)+3;
static volatile  bit	PC2PD		                      @ ((unsigned)&PCPD*8)+2;
static volatile  bit	PC1PD		                      @ ((unsigned)&PCPD*8)+1;
static volatile  bit	PC0PD		                      @ ((unsigned)&PCPD*8)+0;

/* Definitions for PBPD register */
static volatile  bit	PB7PD		                      @ ((unsigned)&PBPD*8)+7;
static volatile  bit	PB6PD		                      @ ((unsigned)&PBPD*8)+6;
static volatile  bit	PB5PD		                      @ ((unsigned)&PBPD*8)+5;
static volatile  bit	PB4PD		                      @ ((unsigned)&PBPD*8)+4;
static volatile  bit	PB3PD		                      @ ((unsigned)&PBPD*8)+3;
static volatile  bit	PB2PD		                      @ ((unsigned)&PBPD*8)+2;
static volatile  bit	PB1PD		                      @ ((unsigned)&PBPD*8)+1;
static volatile  bit	PB0PD		                      @ ((unsigned)&PBPD*8)+0;

/* Definitions for PAPD register */
static volatile  bit	PA5PD		                      @ ((unsigned)&PAPD*8)+5;
static volatile  bit	PA4PD		                      @ ((unsigned)&PAPD*8)+4;
static volatile  bit	PA3PD		                      @ ((unsigned)&PAPD*8)+3;
static volatile  bit	PA2PD		                      @ ((unsigned)&PAPD*8)+2;
static volatile  bit	PA1PD		                      @ ((unsigned)&PAPD*8)+1;
static volatile  bit	PA0PD		                      @ ((unsigned)&PAPD*8)+0;

/* Definitions for PIND register */
static volatile  bit	PIND7	                          @ ((unsigned)&PIND*8)+7;
static volatile  bit	PIND6	                          @ ((unsigned)&PIND*8)+6;
static volatile  bit	PIND5	                          @ ((unsigned)&PIND*8)+5;
static volatile  bit	PIND4	                          @ ((unsigned)&PIND*8)+4;
static volatile  bit	PIND3	                          @ ((unsigned)&PIND*8)+3;
static volatile  bit	PIND2	                          @ ((unsigned)&PIND*8)+2;
static volatile  bit	PIND1	                          @ ((unsigned)&PIND*8)+1;
static volatile  bit	PIND0	                          @ ((unsigned)&PIND*8)+0;
/* Definitions for PINC register */
static volatile  bit	PINC7	                          @ ((unsigned)&PINC*8)+7;
static volatile  bit	PINC6	                          @ ((unsigned)&PINC*8)+6;
static volatile  bit	PINC5	                          @ ((unsigned)&PINC*8)+5;
static volatile  bit	PINC4	                          @ ((unsigned)&PINC*8)+4;
static volatile  bit	PINC3	                          @ ((unsigned)&PINC*8)+3;
static volatile  bit	PINC2	                          @ ((unsigned)&PINC*8)+2;
static volatile  bit	PINC1	                          @ ((unsigned)&PINC*8)+1;
static volatile  bit	PINC0	                          @ ((unsigned)&PINC*8)+0;

/* Definitions for PINB register */
static volatile  bit	PINB7		                      @ ((unsigned)&PINB*8)+7;
static volatile  bit	PINB6		                      @ ((unsigned)&PINB*8)+6;
static volatile  bit	PINB5		                      @ ((unsigned)&PINB*8)+5;
static volatile  bit	PINB4		                      @ ((unsigned)&PINB*8)+4;
static volatile  bit	PINB3		                      @ ((unsigned)&PINB*8)+3;
static volatile  bit	PINB2		                      @ ((unsigned)&PINB*8)+2;
static volatile  bit	PINB1		                      @ ((unsigned)&PINB*8)+1;
static volatile  bit	PINB0		                      @ ((unsigned)&PINB*8)+0;
/* Definitions for PINA register */
static volatile  bit	PINA5		                      @ ((unsigned)&PINA*8)+5;
static volatile  bit	PINA4		                      @ ((unsigned)&PINA*8)+4;
static volatile  bit	PINA3		                      @ ((unsigned)&PINA*8)+3;
static volatile  bit	PINA2		                      @ ((unsigned)&PINA*8)+2;
static volatile  bit	PINA1		                      @ ((unsigned)&PINA*8)+1;
static volatile  bit	PINA0		                      @ ((unsigned)&PINA*8)+0;

/* Definitions for PDPU register */
static volatile  bit	PD7PU		                      @ ((unsigned)&PDPU*8)+7;
static volatile  bit	PD6PU		                      @ ((unsigned)&PDPU*8)+6;
static volatile  bit	PD5PU		                      @ ((unsigned)&PDPU*8)+5;
static volatile  bit	PD4PU		                      @ ((unsigned)&PDPU*8)+4;
static volatile  bit	PD3PU		                      @ ((unsigned)&PDPU*8)+3;
static volatile  bit	PD2PU		                      @ ((unsigned)&PDPU*8)+2;
static volatile  bit	PD1PU		                      @ ((unsigned)&PDPU*8)+1;
static volatile  bit	PD0PU		                      @ ((unsigned)&PDPU*8)+0;

/* Definitions for PCPU register */
static volatile  bit	PC7PU		                      @ ((unsigned)&PCPU*8)+7;
static volatile  bit	PC6PU		                      @ ((unsigned)&PCPU*8)+6;
static volatile  bit	PC5PU		                      @ ((unsigned)&PCPU*8)+5;
static volatile  bit	PC4PU		                      @ ((unsigned)&PCPU*8)+4;
static volatile  bit	PC3PU		                      @ ((unsigned)&PCPU*8)+3;
static volatile  bit	PC2PU		                      @ ((unsigned)&PCPU*8)+2;
static volatile  bit	PC1PU		                      @ ((unsigned)&PCPU*8)+1;
static volatile  bit	PC0PU		                      @ ((unsigned)&PCPU*8)+0;

/* Definitions for PBPU register */
static volatile  bit	PB7PU		                      @ ((unsigned)&PBPU*8)+7;
static volatile  bit	PB6PU		                      @ ((unsigned)&PBPU*8)+6;
static volatile  bit	PB5PU		                      @ ((unsigned)&PBPU*8)+5;
static volatile  bit	PB4PU		                      @ ((unsigned)&PBPU*8)+4;
static volatile  bit	PB3PU		                      @ ((unsigned)&PBPU*8)+3;
static volatile  bit	PB2PU		                      @ ((unsigned)&PBPU*8)+2;
static volatile  bit	PB1PU		                      @ ((unsigned)&PBPU*8)+1;
static volatile  bit	PB0PU		                      @ ((unsigned)&PBPU*8)+0;
/* Definitions for PAPU register */
static volatile  bit	PA5PU		                      @ ((unsigned)&PAPU*8)+5;
static volatile  bit	PA4PU		                      @ ((unsigned)&PAPU*8)+4;
static volatile  bit	PA3PU		                      @ ((unsigned)&PAPU*8)+3;
static volatile  bit	PA2PU		                      @ ((unsigned)&PAPU*8)+2;
static volatile  bit	PA1PU		                      @ ((unsigned)&PAPU*8)+1;
static volatile  bit	PA0PU		                      @ ((unsigned)&PAPU*8)+0;
/* Definitions for PORTD register */
static volatile  bit	PD7	                              @ ((unsigned)&PORTD*8)+7;
static volatile  bit	PD6	                              @ ((unsigned)&PORTD*8)+6;
static volatile  bit	PD5	                              @ ((unsigned)&PORTD*8)+5;
static volatile  bit	PD4	                              @ ((unsigned)&PORTD*8)+4;
static volatile  bit	PD3	                              @ ((unsigned)&PORTD*8)+3;
static volatile  bit	PD2	                              @ ((unsigned)&PORTD*8)+2;
static volatile  bit	PD1	                              @ ((unsigned)&PORTD*8)+1;
static volatile  bit	PD0	                              @ ((unsigned)&PORTD*8)+0;
/* Definitions for PORTC register */
static volatile  bit	PC7	                              @ ((unsigned)&PORTC*8)+7;
static volatile  bit	PC6	                              @ ((unsigned)&PORTC*8)+6;
static volatile  bit	PC5	                              @ ((unsigned)&PORTC*8)+5;
static volatile  bit	PC4	                              @ ((unsigned)&PORTC*8)+4;
static volatile  bit	PC3	                              @ ((unsigned)&PORTC*8)+3;
static volatile  bit	PC2	                              @ ((unsigned)&PORTC*8)+2;
static volatile  bit	PC1	                              @ ((unsigned)&PORTC*8)+1;
static volatile  bit	PC0	                              @ ((unsigned)&PORTC*8)+0;

/* Definitions for PORTB register */
static volatile  bit	PB7		                          @ ((unsigned)&PORTB*8)+7;
static volatile  bit	PB6		                          @ ((unsigned)&PORTB*8)+6;
static volatile  bit	PB5		                          @ ((unsigned)&PORTB*8)+5;
static volatile  bit	PB4		                          @ ((unsigned)&PORTB*8)+4;
static volatile  bit	PB3		                          @ ((unsigned)&PORTB*8)+3;
static volatile  bit	PB2		                          @ ((unsigned)&PORTB*8)+2;
static volatile  bit	PB1		                          @ ((unsigned)&PORTB*8)+1;
static volatile  bit	PB0		                          @ ((unsigned)&PORTB*8)+0;

/* Definitions for PORTA register */
static volatile  bit	PA5		                          @ ((unsigned)&PORTA*8)+5;
static volatile  bit	PA4		                          @ ((unsigned)&PORTA*8)+4;
static volatile  bit	PA3		                          @ ((unsigned)&PORTA*8)+3;
static volatile  bit	PA2		                          @ ((unsigned)&PORTA*8)+2;
static volatile  bit	PA1		                          @ ((unsigned)&PORTA*8)+1;
static volatile  bit	PA0		                          @ ((unsigned)&PORTA*8)+0;

/* Definitions for CMP0CON0 register */
static volatile  bit	CMP0EN                            @ ((unsigned)&CMP0CON0*8)+7;
static volatile  bit	CMP0POS                           @ ((unsigned)&CMP0CON0*8)+6;
static volatile  bit	CMP0PCH2                          @ ((unsigned)&CMP0CON0*8)+5;
static volatile  bit	CMP0PCH1                          @ ((unsigned)&CMP0CON0*8)+4;
static volatile  bit	CMP0PCH0                          @ ((unsigned)&CMP0CON0*8)+3;
static volatile  bit	CMP0NCH2                          @ ((unsigned)&CMP0CON0*8)+2;
static volatile  bit	CMP0NCH1                          @ ((unsigned)&CMP0CON0*8)+1;
static volatile  bit	CMP0NCH0                          @ ((unsigned)&CMP0CON0*8)+0;

/* Definitions for CMP0CON1 register */
static volatile  bit	CMP0HYSEN                         @ ((unsigned)&CMP0CON1*8)+7;
static volatile  bit	CMP0FILTER3                       @ ((unsigned)&CMP0CON1*8)+6;
static volatile  bit	CMP0FILTER2                       @ ((unsigned)&CMP0CON1*8)+5;
static volatile  bit	CMP0FILTER1                       @ ((unsigned)&CMP0CON1*8)+4;
static volatile  bit	CMP0FILTER0                       @ ((unsigned)&CMP0CON1*8)+3;
static volatile  bit	C0OUT1EN                          @ ((unsigned)&CMP0CON1*8)+2;
static volatile  bit	C0OUT0EN                          @ ((unsigned)&CMP0CON1*8)+1;
static volatile  bit	CMP0OUT                           @ ((unsigned)&CMP0CON1*8)+0;

/* Definitions for CMP1CON0 register */
static volatile  bit	CMP1EN                            @ ((unsigned)&CMP1CON0*8)+7;
static volatile  bit	CMP1POS                           @ ((unsigned)&CMP1CON0*8)+6;
static volatile  bit	CMP1PCH2                          @ ((unsigned)&CMP1CON0*8)+5;
static volatile  bit	CMP1PCH1                          @ ((unsigned)&CMP1CON0*8)+4;
static volatile  bit	CMP1PCH0                          @ ((unsigned)&CMP1CON0*8)+3;
static volatile  bit	CMP1NCH2                          @ ((unsigned)&CMP1CON0*8)+2;
static volatile  bit	CMP1NCH1                          @ ((unsigned)&CMP1CON0*8)+1;
static volatile  bit	CMP1NCH0                          @ ((unsigned)&CMP1CON0*8)+0;

/* Definitions for CMP1CON1 register */
static volatile  bit	CMP1HYSEN                        @ ((unsigned)&CMP1CON1*8)+7;
static volatile  bit	CMP1FILTER3                       @ ((unsigned)&CMP1CON1*8)+6;
static volatile  bit	CMP1FILTER2                       @ ((unsigned)&CMP1CON1*8)+5;
static volatile  bit	CMP1FILTER1                       @ ((unsigned)&CMP1CON1*8)+4;
static volatile  bit	CMP1FILTER0                       @ ((unsigned)&CMP1CON1*8)+3;
static volatile  bit	C1OUT1EN                          @ ((unsigned)&CMP1CON1*8)+2;
static volatile  bit	C1OUT0EN                          @ ((unsigned)&CMP1CON1*8)+1;
static volatile  bit	CMP1OUT                           @ ((unsigned)&CMP1CON1*8)+0;

/* Definitions for CMP2CON0 register */
static volatile  bit    CMP2EN                            @ ((unsigned)&CMP2CON0*8)+7;
static volatile  bit    CMP2POS                           @ ((unsigned)&CMP2CON0*8)+6;
static volatile  bit    CMP2PCH2                          @ ((unsigned)&CMP2CON0*8)+5;
static volatile  bit    CMP2PCH1                          @ ((unsigned)&CMP2CON0*8)+4;
static volatile  bit    CMP2PCH0                          @ ((unsigned)&CMP2CON0*8)+3;
static volatile  bit    CMP2NCH2                          @ ((unsigned)&CMP2CON0*8)+2;
static volatile  bit    CMP2NCH1                          @ ((unsigned)&CMP2CON0*8)+1;
static volatile  bit    CMP2NCH0                          @ ((unsigned)&CMP2CON0*8)+0;
/* Definitions for CMP2CON1 register */
static volatile  bit    CMP2HYSEN                        @ ((unsigned)&CMP2CON1*8)+7;
static volatile  bit    CMP2FILTER3                       @ ((unsigned)&CMP2CON1*8)+6;
static volatile  bit    CMP2FILTER2                       @ ((unsigned)&CMP2CON1*8)+5;
static volatile  bit    CMP2FILTER1                       @ ((unsigned)&CMP2CON1*8)+4;
static volatile  bit    CMP2FILTER0                       @ ((unsigned)&CMP2CON1*8)+3;
static volatile  bit    C2OUT1EN                          @ ((unsigned)&CMP2CON1*8)+2;
static volatile  bit    C2OUT0EN                          @ ((unsigned)&CMP2CON1*8)+1;
static volatile  bit    CMP2OUT                           @ ((unsigned)&CMP2CON1*8)+0;

/* Definitions for CMP3CON0 register */
static volatile  bit	CMP3EN                            @ ((unsigned)&CMP3CON0*8)+7;
static volatile  bit	CMP3POS                           @ ((unsigned)&CMP3CON0*8)+6;
static volatile  bit	CMP3PCH2                          @ ((unsigned)&CMP3CON0*8)+5;
static volatile  bit	CMP3PCH1                          @ ((unsigned)&CMP3CON0*8)+4;
static volatile  bit	CMP3PCH0                          @ ((unsigned)&CMP3CON0*8)+3;
static volatile  bit	CMP3NCH2                          @ ((unsigned)&CMP3CON0*8)+2;
static volatile  bit	CMP3NCH1                          @ ((unsigned)&CMP3CON0*8)+1;
static volatile  bit	CMP3NCH0                          @ ((unsigned)&CMP3CON0*8)+0;

/* Definitions for CMP3CON1 register */
static volatile  bit	CMP3_HYSEN                        @ ((unsigned)&CMP3CON1*8)+7;
static volatile  bit	CMP3FILTER3                       @ ((unsigned)&CMP3CON1*8)+6;
static volatile  bit	CMP3FILTER2                       @ ((unsigned)&CMP3CON1*8)+5;
static volatile  bit	CMP3FILTER1                       @ ((unsigned)&CMP3CON1*8)+4;
static volatile  bit	CMP3FILTER0                       @ ((unsigned)&CMP3CON1*8)+3;
static volatile  bit	C3OUT1EN                          @ ((unsigned)&CMP3CON1*8)+2;
static volatile  bit	C3OUT0EN                          @ ((unsigned)&CMP3CON1*8)+1;
static volatile  bit	CMP3OUT                           @ ((unsigned)&CMP3CON1*8)+0;


/* Definitions for DAC1CON register */
static volatile  bit    DAC1VREF                          @ ((unsigned)&DAC1CON*8)+7;
static volatile  bit    DAC1EN	                          @ ((unsigned)&DAC1CON*8)+6;
static volatile  bit    DAC15                             @ ((unsigned)&DAC1CON*8)+5;
static volatile  bit    DAC14                             @ ((unsigned)&DAC1CON*8)+4;
static volatile  bit    DAC13                             @ ((unsigned)&DAC1CON*8)+3;
static volatile  bit    DAC12                             @ ((unsigned)&DAC1CON*8)+2;
static volatile  bit    DAC11                             @ ((unsigned)&DAC1CON*8)+1;
static volatile  bit    DAC10                             @ ((unsigned)&DAC1CON*8)+0;
/* Definitions for DAC0CON register */
static volatile  bit   DAC0VREF                           @ ((unsigned)&DAC0CON*8)+7;
static volatile  bit   DAC0EN	                          @ ((unsigned)&DAC0CON*8)+6;
static volatile  bit   DAC0S5                             @ ((unsigned)&DAC0CON*8)+5;
static volatile  bit   DAC0S4                             @ ((unsigned)&DAC0CON*8)+4;
static volatile  bit   DAC03                              @ ((unsigned)&DAC0CON*8)+3;
static volatile  bit   DAC02                              @ ((unsigned)&DAC0CON*8)+2;
static volatile  bit   DAC01                              @ ((unsigned)&DAC0CON*8)+1;
static volatile  bit   DAC00                              @ ((unsigned)&DAC0CON*8)+0;
/* Definitions for OP0CON0 register */
static volatile  bit   OP0ON                              @ ((unsigned)&OP0CON0*8)+7;
static volatile  bit   EX0	                              @ ((unsigned)&OP0CON0*8)+6;
static volatile  bit   A1NS0                              @ ((unsigned)&OP0CON0*8)+5;
static volatile  bit   PCH02                              @ ((unsigned)&OP0CON0*8)+4;
static volatile  bit   PCH01                              @ ((unsigned)&OP0CON0*8)+3;
static volatile  bit   PCH00                              @ ((unsigned)&OP0CON0*8)+2;
static volatile  bit   NCH01                              @ ((unsigned)&OP0CON0*8)+1;
static volatile  bit   NCH00                              @ ((unsigned)&OP0CON0*8)+0;
/* Definitions for OP0CON1 register */
static volatile  bit   OP0OUT	                          @ ((unsigned)&OP0CON1*8)+7;
static volatile  bit   OUT1EN0	                          @ ((unsigned)&OP0CON1*8)+6;
static volatile  bit   AN_AVSS0                           @ ((unsigned)&OP0CON1*8)+5;
static volatile  bit   A1O2N0	                          @ ((unsigned)&OP0CON1*8)+4;
static volatile  bit   PGAEN0	                          @ ((unsigned)&OP0CON1*8)+3;
static volatile  bit   OP0POS	                          @ ((unsigned)&OP0CON1*8)+2;
static volatile  bit   CMPMODE0                           @ ((unsigned)&OP0CON1*8)+1;
static volatile  bit   OUT0EN0	                          @ ((unsigned)&OP0CON1*8)+0;
/* Definitions for OP0CON2 register */
static volatile  bit   FILTER04                           @ ((unsigned)&OP0CON2*8)+7;
static volatile  bit   FILTER03                           @ ((unsigned)&OP0CON2*8)+6;
static volatile  bit   FILTER02                           @ ((unsigned)&OP0CON2*8)+5;
static volatile  bit   FILTER01                           @ ((unsigned)&OP0CON2*8)+4;
static volatile  bit   FILTER00                           @ ((unsigned)&OP0CON2*8)+3;
static volatile  bit   OP0A2DEN                           @ ((unsigned)&OP0CON2*8)+2;
static volatile  bit   OP0PGA1                            @ ((unsigned)&OP0CON2*8)+1;
static volatile  bit   OP0PGA0	                          @ ((unsigned)&OP0CON2*8)+0;
/* Definitions for OP0CON3 register */
static volatile  bit   OP0_SW0 	                          @ ((unsigned)&OP0CON3*8)+6;
static volatile  bit   OP0_OFFSETEN                       @ ((unsigned)&OP0CON3*8)+5;
static volatile  bit   OP0_OFFSET4                        @ ((unsigned)&OP0CON3*8)+4;
static volatile  bit   OP0_OFFSET3                        @ ((unsigned)&OP0CON3*8)+3;
static volatile  bit   OP0_OFFSET2                        @ ((unsigned)&OP0CON3*8)+2;
static volatile  bit   OP0_OFFSET1                        @ ((unsigned)&OP0CON3*8)+1;
static volatile  bit   OP0_OFFSET0                        @ ((unsigned)&OP0CON3*8)+0;
/* Definitions for OP0CON4 register */
static volatile  bit   OP0CSEL1                           @ ((unsigned)&OP0CON4*8)+1;
static volatile  bit   OP0CSEL0                           @ ((unsigned)&OP0CON4*8)+0;
/* Definitions for FVRCON0  register */
static volatile  bit   FVR_A2D_OUT                        @ ((unsigned)&FVRCON0*8)+7;
static volatile  bit   FVROUTEN                           @ ((unsigned)&FVRCON0*8)+6;
static volatile  bit   FVREN                              @ ((unsigned)&FVRCON0*8)+5;
static volatile  bit   FVRPGA1                            @ ((unsigned)&FVRCON0*8)+4;
static volatile  bit   FVRPGA0                            @ ((unsigned)&FVRCON0*8)+3;
static volatile  bit   FVR_SEL2                           @ ((unsigned)&FVRCON0*8)+2;
static volatile  bit   FVR_SEL1                           @ ((unsigned)&FVRCON0*8)+1;
static volatile  bit   FVR_SEL0                           @ ((unsigned)&FVRCON0*8)+0;
/* Definitions for FVRCON1 register */
static volatile  bit   FVR_OFFSET_EN                      @ ((unsigned)&FVRCON1*8)+5;
static volatile  bit   FVR_TRIM4                          @ ((unsigned)&FVRCON1*8)+4;
static volatile  bit   FVR_TRIM3                          @ ((unsigned)&FVRCON1*8)+3;
static volatile  bit   FVR_TRIM2                          @ ((unsigned)&FVRCON1*8)+2;
static volatile  bit   FVR_TRIM1                          @ ((unsigned)&FVRCON1*8)+1;
static volatile  bit   FVR_TRIM0                          @ ((unsigned)&FVRCON1*8)+0;

/* Definitions for LCDOCN0 register */
static volatile  bit   LCD_DIV4                           @ ((unsigned)&LCDCON0*8)+7;
static volatile  bit   LCD_DIV3                           @ ((unsigned)&LCDCON0*8)+6;
static volatile  bit   LCD_DIV2                           @ ((unsigned)&LCDCON0*8)+5;
static volatile  bit   LCD_DIV1                           @ ((unsigned)&LCDCON0*8)+4;
static volatile  bit   LCD_DIV0                           @ ((unsigned)&LCDCON0*8)+3;
static volatile  bit   PLCDEN                             @ ((unsigned)&LCDCON0*8)+2;
static volatile  bit   LEDEN                              @ ((unsigned)&LCDCON0*8)+1;
static volatile  bit   LCDEN                              @ ((unsigned)&LCDCON0*8)+0;
/* Definitions for LCDOCN1 register */
static volatile  bit   LCDIS1                             @ ((unsigned)&LCDCON1*8)+7;
static volatile  bit   LCDIS0                             @ ((unsigned)&LCDCON1*8)+6;
static volatile  bit   COMSEL2                            @ ((unsigned)&LCDCON1*8)+5;
static volatile  bit   COMSEL1                            @ ((unsigned)&LCDCON1*8)+4;
static volatile  bit   COMSEL0                            @ ((unsigned)&LCDCON1*8)+3;
/* Definitions for COMEN register */
static volatile  bit   COM7EN                             @ ((unsigned)&COMEN*8)+7;
static volatile  bit   COM6EN                             @ ((unsigned)&COMEN*8)+6;
static volatile  bit   COM5EN                             @ ((unsigned)&COMEN*8)+5;
static volatile  bit   COM4EN                             @ ((unsigned)&COMEN*8)+4;
static volatile  bit   COM3EN                             @ ((unsigned)&COMEN*8)+3;
static volatile  bit   COM2EN                             @ ((unsigned)&COMEN*8)+2;
static volatile  bit   COM1EN                             @ ((unsigned)&COMEN*8)+1;
static volatile  bit   COM0EN                             @ ((unsigned)&COMEN*8)+0;
/* Definitions for SEGEN0 register */
static volatile  bit   SEG7EN                             @ ((unsigned)&SEGEN0*8)+7;
static volatile  bit   SEG6EN                             @ ((unsigned)&SEGEN0*8)+6;
static volatile  bit   SEG5EN                             @ ((unsigned)&SEGEN0*8)+5;
static volatile  bit   SEG4EN                             @ ((unsigned)&SEGEN0*8)+4;
static volatile  bit   SEG3EN                             @ ((unsigned)&SEGEN0*8)+3;
static volatile  bit   SEG2EN                             @ ((unsigned)&SEGEN0*8)+2;
static volatile  bit   SEG1EN                             @ ((unsigned)&SEGEN0*8)+1;
static volatile  bit   SEG0EN                             @ ((unsigned)&SEGEN0*8)+0;
/* Definitions for SEGEN1 register */
static volatile  bit   SEG15EN                            @ ((unsigned)&SEGEN1*8)+7;
static volatile  bit   SEG14EN                            @ ((unsigned)&SEGEN1*8)+6;
static volatile  bit   SEG13EN                            @ ((unsigned)&SEGEN1*8)+5;
static volatile  bit   SEG12EN                            @ ((unsigned)&SEGEN1*8)+4;
static volatile  bit   SEG11EN                            @ ((unsigned)&SEGEN1*8)+3;
static volatile  bit   SEG10EN                            @ ((unsigned)&SEGEN1*8)+2;
static volatile  bit   SEG9EN                             @ ((unsigned)&SEGEN1*8)+1;
static volatile  bit   SEG8EN                             @ ((unsigned)&SEGEN1*8)+0;
 /* Definitions for SEGEN2  register */
static volatile  bit   SEGOFF                             @ ((unsigned)&SEGEN2*8)+5;
static volatile  bit   TYPE                               @ ((unsigned)&SEGEN2*8)+4;
static volatile  bit   SEG18EN                            @ ((unsigned)&SEGEN2*8)+2;
static volatile  bit   SEG17EN                            @ ((unsigned)&SEGEN2*8)+1;
static volatile  bit   SEG16EN                            @ ((unsigned)&SEGEN2*8)+0;

/* Definitions for DIVCON register */
static volatile bit    DIV0                               @ ((unsigned)&DIVCON*8)+3;
static volatile bit    COMPLETE                           @ ((unsigned)&DIVCON*8)+2;
static volatile bit    BUSY                               @ ((unsigned)&DIVCON*8)+1;
static volatile bit    START                              @ ((unsigned)&DIVCON*8)+0;

/* Definitions for ADRESH3 register */
static volatile  bit   AD3CH3                             @ ((unsigned)&ADRESH3*8)+7;
static volatile  bit   AD3CH2                             @ ((unsigned)&ADRESH3*8)+6;
static volatile  bit   AD3CH1                             @ ((unsigned)&ADRESH3*8)+5;
static volatile  bit   AD3CH0                             @ ((unsigned)&ADRESH3*8)+4;


/* Definitions for ADRESH2 register */
static volatile  bit   AD2CH3                             @ ((unsigned)&ADRESH2*8)+7;
static volatile  bit   AD2CH2                             @ ((unsigned)&ADRESH2*8)+6;
static volatile  bit   AD2CH1                             @ ((unsigned)&ADRESH2*8)+5;
static volatile  bit   AD2CH0                             @ ((unsigned)&ADRESH2*8)+4;

/* Definitions for ADRESH1 register */
static volatile  bit   AD1CH3                             @ ((unsigned)&ADRESH1*8)+7;
static volatile  bit   AD1CH2                             @ ((unsigned)&ADRESH1*8)+6;
static volatile  bit   AD1CH1                             @ ((unsigned)&ADRESH1*8)+5;
static volatile  bit   AD1CH0                             @ ((unsigned)&ADRESH1*8)+4;

/* Definitions for ADRESH0 register */
static volatile  bit   AD0CH3                             @ ((unsigned)&ADRESH0*8)+7;
static volatile  bit   AD0CH2                             @ ((unsigned)&ADRESH0*8)+6;
static volatile  bit   AD0CH1                             @ ((unsigned)&ADRESH0*8)+5;
static volatile  bit   AD0CH0                             @ ((unsigned)&ADRESH0*8)+4;

/* Definitions for ADCON0 register */
static volatile  bit   ADFM                               @ ((unsigned)&ADCON0*8)+7;
static volatile  bit   ADCMPMODE                          @ ((unsigned)&ADCON0*8)+6;
static volatile  bit   AD3CH4                             @ ((unsigned)&ADCON0*8)+5;
static volatile  bit   AD2CH4                             @ ((unsigned)&ADCON0*8)+4;
static volatile  bit   AD1CH4                             @ ((unsigned)&ADCON0*8)+3;
static volatile  bit   AD0CH4                             @ ((unsigned)&ADCON0*8)+2;
static volatile  bit   GO                                 @ ((unsigned)&ADCON0*8)+1;
static volatile  bit   DONE                               @ ((unsigned)&ADCON0*8)+1;
static volatile  bit   ADON                               @ ((unsigned)&ADCON0*8)+0;
/* Definitions for ADCON1 register */
static volatile  bit   ADCVREF                            @ ((unsigned)&ADCON1*8)+7;
static volatile  bit   ADCSP                              @ ((unsigned)&ADCON1*8)+6;
static volatile  bit   ACQT2                              @ ((unsigned)&ADCON1*8)+5;
static volatile  bit   ACQT1                              @ ((unsigned)&ADCON1*8)+4;
static volatile  bit   ACQT0                              @ ((unsigned)&ADCON1*8)+3;
static volatile  bit   ADCS2                              @ ((unsigned)&ADCON1*8)+2;
static volatile  bit   ADCS1                              @ ((unsigned)&ADCON1*8)+1;
static volatile  bit   ADCS0                              @ ((unsigned)&ADCON1*8)+0;

/* Definitions for ADCON3 register */
static volatile  bit   ADCRPT1                            @ ((unsigned)&ADCON3*8)+4;
static volatile  bit   ADCRPT2                            @ ((unsigned)&ADCON3*8)+3;
static volatile  bit   AD3EN                              @ ((unsigned)&ADCON3*8)+2;
static volatile  bit   AD2EN                              @ ((unsigned)&ADCON3*8)+1;
static volatile  bit   AD1EN                              @ ((unsigned)&ADCON3*8)+0;
/* Definitions for CLKCFG1  register */
static volatile  bit   I2CCLKEN                           @ ((unsigned)&CLKCFG1*8)+7;
static volatile  bit   UART1CLKEN                         @ ((unsigned)&CLKCFG1*8)+6;
static volatile  bit   UART0CLKEN                         @ ((unsigned)&CLKCFG1*8)+5;
static volatile  bit   CCPCLKEN                           @ ((unsigned)&CLKCFG1*8)+4;
static volatile  bit   T3CLKEN                            @ ((unsigned)&CLKCFG1*8)+3;
static volatile  bit   T2CLKEN                            @ ((unsigned)&CLKCFG1*8)+2;
static volatile  bit   T1CLKEN                            @ ((unsigned)&CLKCFG1*8)+1;
static volatile  bit   T0CLKEN                            @ ((unsigned)&CLKCFG1*8)+0;
/* Definitions for CLKCFG2 register */
static volatile  bit   SPICLKEN                           @ ((unsigned)&CLKCFG2*8)+7;
static volatile  bit   CMP2CLKEN                          @ ((unsigned)&CLKCFG2*8)+4;
static volatile  bit   DACCLKEN                           @ ((unsigned)&CLKCFG2*8)+3;
static volatile  bit   ADCCLKEN                           @ ((unsigned)&CLKCFG2*8)+2;
static volatile  bit   CMPCLKEN                           @ ((unsigned)&CLKCFG2*8)+1;
static volatile  bit   OPCLKEN                            @ ((unsigned)&CLKCFG2*8)+0;
 /* Definitions for PAINTMASK register */
static volatile  bit   PA5MSK                             @ ((unsigned)&PAINTMASK*8)+5;
static volatile  bit   PA4MSK                             @ ((unsigned)&PAINTMASK*8)+4;
static volatile  bit   PA3MSK                             @ ((unsigned)&PAINTMASK*8)+3;
static volatile  bit   PA2MSK                             @ ((unsigned)&PAINTMASK*8)+2;
static volatile  bit   PA1MSK                             @ ((unsigned)&PAINTMASK*8)+1;
static volatile  bit   PA0MSK                             @ ((unsigned)&PAINTMASK*8)+0;
/* Definitions for PBINTMASK register */
static volatile  bit   PB7MSK                             @ ((unsigned)&PBINTMASK*8)+7;
static volatile  bit   PB6MSK                             @ ((unsigned)&PBINTMASK*8)+6;
static volatile  bit   PB5MSK                             @ ((unsigned)&PBINTMASK*8)+5;
static volatile  bit   PB4MSK                             @ ((unsigned)&PBINTMASK*8)+4;
static volatile  bit   PB3MSK                             @ ((unsigned)&PBINTMASK*8)+3;
static volatile  bit   PB2MSK                             @ ((unsigned)&PBINTMASK*8)+2;
static volatile  bit   PB1MSK                             @ ((unsigned)&PBINTMASK*8)+1;
static volatile  bit   PB0MSK                             @ ((unsigned)&PBINTMASK*8)+0;
/* Definitions for PCINTMASK register */
static volatile  bit   PC7MSK                             @ ((unsigned)&PCINTMASK*8)+7;
static volatile  bit   PC6MSK                             @ ((unsigned)&PCINTMASK*8)+6;
static volatile  bit   PC5MSK                             @ ((unsigned)&PCINTMASK*8)+5;
static volatile  bit   PC4MSK                             @ ((unsigned)&PCINTMASK*8)+4;
static volatile  bit   PC3MSK                             @ ((unsigned)&PCINTMASK*8)+3;
static volatile  bit   PC2MSK                             @ ((unsigned)&PCINTMASK*8)+2;
static volatile  bit   PC1MSK                             @ ((unsigned)&PCINTMASK*8)+1;
static volatile  bit   PC0MSK                             @ ((unsigned)&PCINTMASK*8)+0;
/* Definitions for PDINTMASK register */
static volatile  bit   PD7MSK                             @ ((unsigned)&PDINTMASK*8)+7;
static volatile  bit   PD6MSK                             @ ((unsigned)&PDINTMASK*8)+6;
static volatile  bit   PD5MSK                             @ ((unsigned)&PDINTMASK*8)+5;
static volatile  bit   PD4MSK                             @ ((unsigned)&PDINTMASK*8)+4;
static volatile  bit   PD3MSK                             @ ((unsigned)&PDINTMASK*8)+3;
static volatile  bit   PD2MSK                             @ ((unsigned)&PDINTMASK*8)+2;
static volatile  bit   PD1MSK                             @ ((unsigned)&PDINTMASK*8)+1;
static volatile  bit   PD0MSK                             @ ((unsigned)&PDINTMASK*8)+0;
/* Definitions for  EECON1 register */
static volatile  bit   ER16EN                             @ ((unsigned)&EECON1*8)+6;
static volatile  bit   ERBEN                              @ ((unsigned)&EECON1*8)+5;
static volatile  bit   WRBEN                              @ ((unsigned)&EECON1*8)+4;
static volatile  bit   WERR                               @ ((unsigned)&EECON1*8)+3;
static volatile  bit   WREN                               @ ((unsigned)&EECON1*8)+2;
static volatile  bit   WR                                 @ ((unsigned)&EECON1*8)+1;
static volatile  bit   RD                                 @ ((unsigned)&EECON1*8)+0;
/* Definitions for IAPCTRL register */
static volatile  bit	ERR 		                      @ ((unsigned)&IAPCTRL*8)+3;
static volatile  bit	LOCK 		                      @ ((unsigned)&IAPCTRL*8)+2;
static volatile  bit	ER  		                      @ ((unsigned)&IAPCTRL*8)+1;
static volatile  bit	PG	    	                      @ ((unsigned)&IAPCTRL*8)+0;

/* Definitions for TXSTA0  register */

static volatile  bit   CSRC 			                  @ ((unsigned)&TXSTA*8)+7;
static volatile  bit   TX9		   	                      @ ((unsigned)&TXSTA*8)+6;
static volatile  bit   TXEN			                      @ ((unsigned)&TXSTA*8)+5;
static volatile  bit   SYNC			                      @ ((unsigned)&TXSTA*8)+4;
static volatile  bit   TX_PARITY		                  @ ((unsigned)&TXSTA*8)+3;
static volatile  bit   BRGH		     	                  @ ((unsigned)&TXSTA*8)+2;
static volatile  bit   TMRT		 	                      @ ((unsigned)&TXSTA*8)+1;
static volatile  bit   TX9D 			                  @ ((unsigned)&TXSTA*8)+0;

/* Definitions for RCSTA0  register */
static volatile  bit   SPEN 			                   @ ((unsigned)&RCSTA*8)+7;
static volatile  bit   RX09		   	                       @ ((unsigned)&RCSTA*8)+6;
static volatile  bit   SREN	   		                       @ ((unsigned)&RCSTA*8)+5;
static volatile  bit   CREN				                   @ ((unsigned)&RCSTA*8)+4;
static volatile  bit   BGRM	     		                   @ ((unsigned)&RCSTA*8)+3;
static volatile  bit   FERR				                   @ ((unsigned)&RCSTA*8)+2;
static volatile  bit   OERR				                   @ ((unsigned)&RCSTA*8)+1;
static volatile  bit   RX9D				                   @ ((unsigned)&RCSTA*8)+0;
/* Definitions for UARTCON  register */
static volatile  bit   INVMODE		                   	  @ ((unsigned)&UARTCON*8)+7;
static volatile  bit   PARITY	                          @ ((unsigned)&UARTCON*8)+6;
static volatile  bit   ODD_EVEN		        	 		  @ ((unsigned)&UARTCON*8)+5;
static volatile  bit   BCLK		                 	 	  @ ((unsigned)&UARTCON*8)+4;
static volatile  bit   HALF_DUPLEX	                   	  @ ((unsigned)&UARTCON*8)+3;
static volatile  bit   DLSB   		                	  @ ((unsigned)&UARTCON*8)+2;
static volatile  bit   STOP_BIT1		                  @ ((unsigned)&UARTCON*8)+1;
static volatile  bit   STOP_BIT0		                  @ ((unsigned)&UARTCON*8)+0;
//* Definitions for TXSTA1  register */

static volatile  bit   CSRC1			                  @ ((unsigned)&TXSTA1*8)+7;
static volatile  bit   TX19		   	                      @ ((unsigned)&TXSTA1*8)+6;
static volatile  bit   TX1EN1			                  @ ((unsigned)&TXSTA1*8)+5;
static volatile  bit   SYNC1			                  @ ((unsigned)&TXSTA1*8)+4;
static volatile  bit   TX1_PARITY		                  @ ((unsigned)&TXSTA1*8)+3;
static volatile  bit   BRGH1			                  @ ((unsigned)&TXSTA1*8)+2;
static volatile  bit   TMRT1			                  @ ((unsigned)&TXSTA1*8)+1;
static volatile  bit   TX19D			                  @ ((unsigned)&TXSTA1*8)+0;
/* Definitions for RCSTA1 register */
static volatile  bit   SPEN1			                  @ ((unsigned)&RCSTA1*8)+7;
static volatile  bit   RX19		   	                      @ ((unsigned)&RCSTA1*8)+6;
static volatile  bit   SREN1			                  @ ((unsigned)&RCSTA1*8)+5;
static volatile  bit   CREN1			                  @ ((unsigned)&RCSTA1*8)+4;
static volatile  bit   BGRM1      		                  @ ((unsigned)&RCSTA1*8)+3;
static volatile  bit   FERR1			                  @ ((unsigned)&RCSTA1*8)+2;
static volatile  bit   OERR1			                  @ ((unsigned)&RCSTA1*8)+1;
static volatile  bit   RX19D			                  @ ((unsigned)&RCSTA1*8)+0;
/* Definitions for UARTCON1  register */
static volatile  bit   INVMODE1		                      @ ((unsigned)&UARTCON1*8)+7;
static volatile  bit   PARITY1	                          @ ((unsigned)&UARTCON1*8)+6;
static volatile  bit   ODD1_EVEN		              	  @ ((unsigned)&UARTCON1*8)+5;
static volatile  bit   BCLK1		               	      @ ((unsigned)&UARTCON1*8)+4;
static volatile  bit   HALF1_DUPLEX	                      @ ((unsigned)&UARTCON1*8)+3;
static volatile  bit   DLSB1    		                  @ ((unsigned)&UARTCON1*8)+2;
static volatile  bit   STOP1_BIT1		                  @ ((unsigned)&UARTCON1*8)+1;
static volatile  bit   STOP1_BIT0		                  @ ((unsigned)&UARTCON1*8)+0;
/* Definitions for I2CACKDLY register */
static volatile bit     ACKDLYON                          @ ((unsigned)&I2CACKDLY*8)+7;
static volatile bit     ACKDLY6        	                  @ ((unsigned)&I2CACKDLY*8)+6;
static volatile bit     ACKDLY5    		                  @ ((unsigned)&I2CACKDLY*8)+5;
static volatile bit     ACKDLY4    		                  @ ((unsigned)&I2CACKDLY*8)+4;
static volatile bit     ACKDLY3                           @ ((unsigned)&I2CACKDLY*8)+3;
static volatile bit     ACKDLY2    		                  @ ((unsigned)&I2CACKDLY*8)+2;
static volatile bit     ACKDLY1    		                  @ ((unsigned)&I2CACKDLY*8)+1;
static volatile bit     ACKDLY0    		                  @ ((unsigned)&I2CACKDLY*8)+0;
/* Definitions for I2CSTAT register */
static volatile bit     I2C_A     		                  @ ((unsigned)&I2CSTAT*8)+5;
static volatile bit     I2C_D   		                  @ ((unsigned)&I2CSTAT*8)+5;
static volatile bit     P       		                  @ ((unsigned)&I2CSTAT*8)+4;
static volatile bit     S                                 @ ((unsigned)&I2CSTAT*8)+3;
static volatile bit     R        		                  @ ((unsigned)&I2CSTAT*8)+2;
static volatile bit     W      		                      @ ((unsigned)&I2CSTAT*8)+2;
static volatile bit     BPRX    		                  @ ((unsigned)&I2CSTAT*8)+1;
static volatile bit     BPTX    		                  @ ((unsigned)&I2CSTAT*8)+0;
/* Definitions for I2CCON0 register */
static volatile bit     I2C_WCOL    		              @ ((unsigned)&I2CCON0*8)+7;
static volatile bit     I2COV    		                  @ ((unsigned)&I2CCON0*8)+6;
static volatile bit     I2CEN                             @ ((unsigned)&I2CCON0*8)+5;
static volatile bit     I2STEN        		              @ ((unsigned)&I2CCON0*8)+4;

/* Definitions for I2CCON1 register */
static volatile bit     GCEN                              @ ((unsigned)&I2CCON1*8)+7;
static volatile bit     ACKSTAT        	                  @ ((unsigned)&I2CCON1*8)+6;
static volatile bit     ACKGET 		                  	  @ ((unsigned)&I2CCON1*8)+5;
static volatile bit     ACKEN      		                  @ ((unsigned)&I2CCON1*8)+4;
/* Definitions for I2CIE register */
static volatile bit     I2C_FLOATIE                    	  @ ((unsigned)&I2CIE*8)+4;
static volatile bit     I2C_STOPIE        		          @ ((unsigned)&I2CIE*8)+3;
static volatile bit     I2C_STATRIE      	           	  @ ((unsigned)&I2CIE*8)+2;
static volatile bit     I2C_TXIE                       	  @ ((unsigned)&I2CIE*8)+1;
static volatile bit     I2C_RCIE                       	  @ ((unsigned)&I2CIE*8)+0;
/* Definitions for I2CIF register */
static volatile bit     I2C_FLOATIF		                  @ ((unsigned)&I2CIF*8)+4;
static volatile bit     I2C_STOPIF        		          @ ((unsigned)&I2CIF*8)+3;
static volatile bit     I2C_STATRIF      	           	  @ ((unsigned)&I2CIF*8)+2;
static volatile bit     I2C_TXIF                       	  @ ((unsigned)&I2CIF*8)+1;
static volatile bit     I2C_RCIF                          @ ((unsigned)&I2CIF*8)+0;
/* Definitions for I2CIP register */
static volatile bit     I2C_FLOATIP                       @ ((unsigned)&I2CIP*8)+4;
static volatile bit     I2C_STOPIP        		       	  @ ((unsigned)&I2CIP*8)+3;
static volatile bit     I2C_STATRIP      	           	  @ ((unsigned)&I2CIP*8)+2;
static volatile bit     I2C_TXIP                       	  @ ((unsigned)&I2CIP*8)+1;
static volatile bit     I2C_RCIP     	                  @ ((unsigned)&I2CIP*8)+0;
/* Definitions for SPCON  register */
static volatile  bit   SPIR2                              @ ((unsigned)&SPCON*8)+7;
static volatile  bit   SPIEN        	                  @ ((unsigned)&SPCON*8)+6;
static volatile  bit   SSDIS     	                   	  @ ((unsigned)&SPCON*8)+5;
static volatile  bit   MSTR       		              	  @ ((unsigned)&SPCON*8)+4;
static volatile  bit   CPOL                            	  @ ((unsigned)&SPCON*8)+3;
static volatile  bit   CPHA      		               	  @ ((unsigned)&SPCON*8)+2;
static volatile  bit   SPIR1    		               	  @ ((unsigned)&SPCON*8)+1;
static volatile  bit   SPIR0    		               	  @ ((unsigned)&SPCON*8)+0;
/* Definitions for  SPSTA  register */
static volatile  bit   SPI_MAP0                           @ ((unsigned)&SPSTA*8)+0;
static volatile  bit   SPI_MAP1                           @ ((unsigned)&SPSTA*8)+1;
static volatile  bit   SPINSS_MAP0    	                  @ ((unsigned)&SPSTA*8)+2;
static volatile  bit   SPINSS_MAP1                        @ ((unsigned)&SPSTA*8)+3;
static volatile  bit   MODF      		                  @ ((unsigned)&SPSTA*8)+4;
static volatile  bit   SSERR                              @ ((unsigned)&SPSTA*8)+5;
static volatile  bit   WCOL    		                      @ ((unsigned)&SPSTA*8)+6;

/* Definitions for OSCCON  register */
static volatile  bit   FINTOSC2                          @ ((unsigned)&OSCCON*8)+7;
static volatile  bit   FINTOSC1                          @ ((unsigned)&OSCCON*8)+6;
static volatile  bit   FINTOSC0                          @ ((unsigned)&OSCCON*8)+5;
static volatile  bit   CKOE                              @ ((unsigned)&OSCCON*8)+4;
static volatile  bit   OSCF1      		                 @ ((unsigned)&OSCCON*8)+3;
static volatile  bit   OSCF0    		                 @ ((unsigned)&OSCCON*8)+2;
static volatile  bit   OSCM1                             @ ((unsigned)&OSCCON*8)+1;
static volatile  bit   OSCM0            	             @ ((unsigned)&OSCCON*8)+0;
/* Definitions for SIGCON  register */
static volatile  bit   OP_HYS_EN                         @ ((unsigned)&SIGCON*8)+7;
static volatile  bit   PLL                               @ ((unsigned)&SIGCON*8)+6;
static volatile  bit   LXTL_SEEPUP                       @ ((unsigned)&SIGCON*8)+5;
static volatile  bit   ENVDDL                            @ ((unsigned)&SIGCON*8)+1;
static volatile  bit   SIGS                              @ ((unsigned)&SIGCON*8)+0;
/* Definitions for SMCR  register */
static volatile  bit   SM2                               @ ((unsigned)&SMCR*8)+3;
static volatile  bit   SM1                               @ ((unsigned)&SMCR*8)+2;
static volatile  bit   SM0                               @ ((unsigned)&SMCR*8)+1;
static volatile  bit   SE                                @ ((unsigned)&SMCR*8)+0;
/* Definitions for PDSINKCUR  register */
static volatile  bit   PD7SCUR                           @ ((unsigned)&PDSINKCUR*8)+7;
static volatile  bit   PD6SCUR                           @ ((unsigned)&PDSINKCUR*8)+6;
static volatile  bit   PD5SCUR                           @ ((unsigned)&PDSINKCUR*8)+5;
static volatile  bit   PD4SCUR                           @ ((unsigned)&PDSINKCUR*8)+4;
static volatile  bit   PD3SCUR      		             @ ((unsigned)&PDSINKCUR*8)+3;
static volatile  bit   PD2SCUR    	                     @ ((unsigned)&PDSINKCUR*8)+2;
static volatile  bit   PD1SCUR    	                     @ ((unsigned)&PDSINKCUR*8)+1;
static volatile  bit   PD0SCUR   		                 @ ((unsigned)&PDSINKCUR*8)+0;
/* Definitions for CURCON  register */
static volatile  bit   PCCUR1           	             @ ((unsigned)&CURCON*8)+5;
static volatile  bit   PCCUR0       	                 @ ((unsigned)&CURCON*8)+4;
static volatile  bit   PBCUR1                            @ ((unsigned)&CURCON*8)+3;
static volatile  bit   PBCUR0      	                     @ ((unsigned)&CURCON*8)+2;
static volatile  bit   PACUR1    	                     @ ((unsigned)&CURCON*8)+1;
static volatile  bit   PACUR0   		                 @ ((unsigned)&CURCON*8)+0;
 /* Definitions for TX0_MAP  register */
static volatile  bit   TX0_MPORT1                        @ ((unsigned)&TX0_MAP*8)+4;
static volatile  bit   TX0_MPORT0                        @ ((unsigned)&TX0_MAP*8)+3;
static volatile  bit   TX0_MPIN2                         @ ((unsigned)&TX0_MAP*8)+2;
static volatile  bit   TX0_MPIN1                         @ ((unsigned)&TX0_MAP*8)+1;
static volatile  bit   TX0_MPIN0                         @ ((unsigned)&TX0_MAP*8)+0;
/* Definitions for RX0_MAP  register */
static volatile  bit   RX0_MPORT1                        @ ((unsigned)&RX0_MAP*8)+4;
static volatile  bit   RX0_MPORT0                        @ ((unsigned)&RX0_MAP*8)+3;
static volatile  bit   RX0_MPIN2                         @ ((unsigned)&RX0_MAP*8)+2;
static volatile  bit   RX0_MPIN1                         @ ((unsigned)&RX0_MAP*8)+1;
static volatile  bit   RX0_MPIN0                         @ ((unsigned)&RX0_MAP*8)+0;
/* Definitions for TX1_MAP  register */
static volatile  bit   TX1_MPORT1                        @ ((unsigned)&TX1_MAP*8)+4;
static volatile  bit   TX1_MPORT0                        @ ((unsigned)&TX1_MAP*8)+3;
static volatile  bit   TX1_MPIN2                         @ ((unsigned)&TX1_MAP*8)+2;
static volatile  bit   TX1_MPIN1                         @ ((unsigned)&TX1_MAP*8)+1;
static volatile  bit   TX1_MPIN0                         @ ((unsigned)&TX1_MAP*8)+0;
/* Definitions for RX1_MAP  register */
static volatile  bit   RX1_MPORT1                        @ ((unsigned)&RX1_MAP*8)+4;
static volatile  bit   RX1_MPORT0                        @ ((unsigned)&RX1_MAP*8)+3;
static volatile  bit   RX1_MPIN2                         @ ((unsigned)&RX1_MAP*8)+2;
static volatile  bit   RX1_MPIN1                         @ ((unsigned)&RX1_MAP*8)+1;
static volatile  bit   RX1_MPIN0                         @ ((unsigned)&RX1_MAP*8)+0;
 /* Definitions for SDA_MAP  register */
static volatile  bit   SDA_MPORT1                        @ ((unsigned)&SDA_MAP*8)+4;
static volatile  bit   SDA_MPORT0                        @ ((unsigned)&SDA_MAP*8)+3;
static volatile  bit   SDA_MPIN2                         @ ((unsigned)&SDA_MAP*8)+2;
static volatile  bit   SDA_MPIN1                         @ ((unsigned)&SDA_MAP*8)+1;
static volatile  bit   SDA_MPIN0                         @ ((unsigned)&SDA_MAP*8)+0;
/* Definitions for SCL_MAP  register */
static volatile  bit   SCL_MPORT1                        @ ((unsigned)&SCL_MAP*8)+4;
static volatile  bit   SCL_MPORT0                        @ ((unsigned)&SCL_MAP*8)+3;
static volatile  bit   SCL_MPIN2                         @ ((unsigned)&SCL_MAP*8)+2;
static volatile  bit   SCL_MPIN1                         @ ((unsigned)&SCL_MAP*8)+1;
static volatile  bit   SCL_MPIN0                         @ ((unsigned)&SCL_MAP*8)+0;
 /* Definitions for PWM0_MAP register */
static volatile  bit   PWM0_MPORT1                       @ ((unsigned)&PWM0_MAP*8)+4;
static volatile  bit   PWM0_MPORT0                       @ ((unsigned)&PWM0_MAP*8)+3;
static volatile  bit   PWM0_MPIN2                        @ ((unsigned)&PWM0_MAP*8)+2;
static volatile  bit   PWM0_MPIN1                        @ ((unsigned)&PWM0_MAP*8)+1;
static volatile  bit   PWM0_MPIN0                        @ ((unsigned)&PWM0_MAP*8)+0;
/* Definitions for PWM00_MAP  register */
static volatile  bit   PWM00_MPORT1                      @ ((unsigned)&PWM00_MAP*8)+4;
static volatile  bit   PWM00_MPORT0                      @ ((unsigned)&PWM00_MAP*8)+3;
static volatile  bit   PWM00_MPIN2                       @ ((unsigned)&PWM00_MAP*8)+2;
static volatile  bit   PWM00_MPIN1                       @ ((unsigned)&PWM00_MAP*8)+1;
static volatile  bit   PWM00_MPIN0                       @ ((unsigned)&PWM00_MAP*8)+0;
/* Definitions for PWM01_MAP  register */
static volatile  bit   PWM01_MPORT1                      @ ((unsigned)&PWM01_MAP*8)+4;
static volatile  bit   PWM01_MPORT0                      @ ((unsigned)&PWM01_MAP*8)+3;
static volatile  bit   PWM01_MPIN2                       @ ((unsigned)&PWM01_MAP*8)+2;
static volatile  bit   PWM01_MPIN1                       @ ((unsigned)&PWM01_MAP*8)+1;
static volatile  bit   PWM01_MPIN0                       @ ((unsigned)&PWM01_MAP*8)+0;
/* Definitions for PWM10_MAP register */
static volatile  bit   PWM10_MPORT1                      @ ((unsigned)&PWM10_MAP*8)+4;
static volatile  bit   PWM10_MPORT0                      @ ((unsigned)&PWM10_MAP*8)+3;
static volatile  bit   PWM10_MPIN2                       @ ((unsigned)&PWM10_MAP*8)+2;
static volatile  bit   PWM10_MPIN1                       @ ((unsigned)&PWM10_MAP*8)+1;
static volatile  bit   PWM10_MPIN0                       @ ((unsigned)&PWM10_MAP*8)+0;
/* Definitions for PWM11_MAP  register */
static volatile  bit   PWM11_MPORT1                      @ ((unsigned)&PWM11_MAP*8)+4;
static volatile  bit   PWM11_MPORT0                      @ ((unsigned)&PWM11_MAP*8)+3;
static volatile  bit   PWM11_MPIN2                       @ ((unsigned)&PWM11_MAP*8)+2;
static volatile  bit   PWM11_MPIN1                       @ ((unsigned)&PWM11_MAP*8)+1;
static volatile  bit   PWM11_MPIN0                       @ ((unsigned)&PWM11_MAP*8)+0;
/* Definitions for PWM20_MAP register */
static volatile  bit   PWM20_MPORT1                      @ ((unsigned)&PWM20_MAP*8)+4;
static volatile  bit   PWM20_MPORT0                      @ ((unsigned)&PWM20_MAP*8)+3;
static volatile  bit   PWM20_MPIN2                       @ ((unsigned)&PWM20_MAP*8)+2;
static volatile  bit   PWM20_MPIN1                       @ ((unsigned)&PWM20_MAP*8)+1;
static volatile  bit   PWM20_MPIN0                       @ ((unsigned)&PWM20_MAP*8)+0;
/* Definitions for PWM21_MAP  register */
static volatile  bit   PWM21_MPORT1                      @ ((unsigned)&PWM21_MAP*8)+4;
static volatile  bit   PWM21_MPORT0                      @ ((unsigned)&PWM21_MAP*8)+3;
static volatile  bit   PWM21_MPIN2                       @ ((unsigned)&PWM21_MAP*8)+2;
static volatile  bit   PWM21_MPIN1                       @ ((unsigned)&PWM21_MAP*8)+1;
static volatile  bit   PWM21_MPIN0                       @ ((unsigned)&PWM21_MAP*8)+0;
/* Definitions for PWM2_MAP  register */
static volatile  bit   PWM2_MPORT1                       @ ((unsigned)&PWM2_MAP*8)+4;
static volatile  bit   PWM2_MPORT0                       @ ((unsigned)&PWM2_MAP*8)+3;
static volatile  bit   PWM2_MPIN2                        @ ((unsigned)&PWM2_MAP*8)+2;
static volatile  bit   PWM2_MPIN1                        @ ((unsigned)&PWM2_MAP*8)+1;
static volatile  bit   PWM2_MPIN0                        @ ((unsigned)&PWM2_MAP*8)+0;

/* Definitions for PWM3_MAP  register */
static volatile  bit   PWM3_MPORT1                       @ ((unsigned)&PWM3_MAP*8)+4;
static volatile  bit   PWM3_MPORT0                       @ ((unsigned)&PWM3_MAP*8)+3;
static volatile  bit   PWM3_MPIN2                        @ ((unsigned)&PWM3_MAP*8)+2;
static volatile  bit   PWM3_MPIN1                        @ ((unsigned)&PWM3_MAP*8)+1;
static volatile  bit   PWM3_MPIN0                        @ ((unsigned)&PWM3_MAP*8)+0;
/* Definitions for PWM4_MAP  register */
static volatile  bit   PWM4_MPORT1                       @ ((unsigned)&PWM4_MAP*8)+4;
static volatile  bit   PWM4_MPORT0                       @ ((unsigned)&PWM4_MAP*8)+3;
static volatile  bit   PWM4_MPIN2                        @ ((unsigned)&PWM4_MAP*8)+2;
static volatile  bit   PWM4_MPIN1                        @ ((unsigned)&PWM4_MAP*8)+1;
static volatile  bit   PWM4_MPIN0                        @ ((unsigned)&PWM4_MAP*8)+0;
/* Definitions for PWM5_MAP  register */
static volatile  bit   PWM5_MPORT1                       @ ((unsigned)&PWM5_MAP*8)+4;
static volatile  bit   PWM5_MPORT0                       @ ((unsigned)&PWM5_MAP*8)+3;
static volatile  bit   PWM5_MPIN2                        @ ((unsigned)&PWM5_MAP*8)+2;
static volatile  bit   PWM5_MPIN1                        @ ((unsigned)&PWM5_MAP*8)+1;
static volatile  bit   PWM5_MPIN0                        @ ((unsigned)&PWM5_MAP*8)+0;



#define ROMSIZE 64 * 1024
#define RAMSIZE 256

#define EEPROM_SIZE 256

/* Macros to access bytes within words and words within longs */
#define LOW_BYTE(x)     ((unsigned char)((x)&0xFF))
#define HIGH_BYTE(x)    ((unsigned char)(((x)>>8)&0xFF))
#define LOW_WORD(x)     ((unsigned short)((x)&0xFFFF))
#define HIGH_WORD(x)    ((unsigned short)(((x)>>16)&0xFFFF))

/* C access to assembler insructions */
#define	CLRWDT()	    asm(" clrwdt")
#define	NOP()		    asm(" nop")
#define	RESET()		    asm(" reset")
#define SLEEP()		    asm(" sleep")

#define	___mkstr1(x)	#x
#define	___mkstr(x)	___mkstr1(x)

/* Store a word value to a particular configuration word register eg.
 * __CONFIG(4, DEBUGEN & LVPDIS); // write to config word 4
 * config mask attributes (such as DEBUGEN) defined in chip-specific
 * header file. */
#define	__CONFIG(n, x)	asm("\tpsect config,class=CONFIG");\
			asm("global config_word" ___mkstr(n)); \
			asm("\torg ("___mkstr(n)"-1)*2"); \
			asm("config_word" ___mkstr(n)":"); \
			asm("\tdw "___mkstr(x))


#define __IDLOC(w)      asm("\tpsect idloc,class=IDLOC");\
			asm("\tglobal\tidloc_word"); \
			asm("idloc_word:"); \
			asm("\tirpc\t__arg," ___mkstr(w)); \
			asm("\tdb 0f&__arg&h"); \
			asm("\tendm")


/* Address definitions for config word registers
 * (NOT TO BE USED WITH __CONFIG MACRO!) */
#define CONFIG1L	0x300000
#define CONFIG1H	0x300001
#define CONFIG2L	0x300002
#define CONFIG2H	0x300003
#define CONFIG3L	0x300004
#define CONFIG3H	0x300005
#define CONFIG4L	0x300006
#define CONFIG4H	0x300007
#define CONFIG5L	0x300008
#define CONFIG5H	0x300009
#define CONFIG6L	0x30000A
#define CONFIG6H	0x30000B
#define CONFIG7L	0x30000C
#define CONFIG7H	0x30000D

//;----- CONFIG0 Options --------------------------------------------------------
#define   _LVR20V_1L              0xFFF0     // LVR_OUT Reset set to 2.0V
#define   _LVR21V_1L              0xFFF1     // LVR_OUT Reset set to 2.1V
#define   _LVR22V_1L              0xFFF2     // LVR_OUT Reset set to 2.2V
#define   _LVR24V_1L              0xFFF3     // LVR_OUT Reset set to 2.4V
#define   _LVR26V_1L              0xFFF4     // LVR_OUT Reset set to 2.6V
#define   _LVR27V_1L              0xFFF5     // LVR_OUT Reset set to 2.7V
#define   _LVR29V_1L              0xFFF6     // LVR_OUT Reset set to 2.9V
#define   _LVR30V_1L              0xFFF7     // LVR_OUT Reset set to 3.0V
#define   _LVR31V_1L              0xFFF8     // LVR_OUT Reset set to 3.1V
#define   _LVR33V_1L              0xFFF9     // LVR_OUT Reset set to 3.3V
#define   _LVR36V_1L              0xFFFA     // LVR_OUT Reset set to 3.6V
#define   _LVR37V_1L              0xFFFB     // LVR_OUT Reset set to 3.7V
#define   _LVR38V_1L              0xFFFC     // LVR_OUT Reset set to 3.8V
#define   _LVR41V_1L              0xFFFD     // LVR_OUT Reset set to 4.1V
#define   _LVR42V_1L              0xFFFE     // LVR_OUT Reset set to 4.2V
#define   _LVR43V_1L              0xFFFF     // LVR_OUT Reset set to 4.3V


#define   _LVREN_ON_1L            0xFFFF    //  Enable LVR reset
#define   _LVREN_OFF_1L           0xFFEF    //  Disable LVR reset

#define   _FINTOSC_DIV1_1L        0xFFFF     // Fosc DIVIDER 1:1
#define   _FINTOSC_DIV2_1L        0xFFDF     // Fosc DIVIDER 1:2
#define   _FINTOSC_DIV4_1L        0xFFBF     // Fosc DIVIDER 1:4
#define   _FINTOSC_DIV8_1L        0xFF9F     // Fosc DIVIDER 1:8
#define   _FINTOSC_DIV16_1L       0xFF5F     // Fosc DIVIDER 1:16

//;----- CONFIG1 Options --------------------------------------------------------
#define  _STV_OFF_2L              0xFFFE		//	Stack overflow reset disable
#define  _STV_ON_2L               0xFFFF		//  Stack overflow reset enable

#define _RSEL_HIGH_2L             0xFFFD		//  pullup 190K,pulldown 300K
#define _RSEL_LOW_2L              0xFFFF		//  pullup  30K, pulldown 30K

#define _RESETE_ON_2L             0xFFFF		//  Reset Pin enable
#define _RESETE_OFF_2L            0xFFFB		//	Reset Pin disable

#define _CBP_ON_2L                0xFFFF		//	Program code encrypte enable
#define _CBP_OFF_2L               0xFFF7		//  Program code encrypte disable

#define _CKSUM_OFF_2L             0xFFEF		//	cksum  disable
#define _CKSUM_ON_2L              0xFFFF		//  cksum  enable

#define _IDIS_OFF_2L              0xFFDF		//	Read  data is always 0
#define _IDIS_ON_2L               0xFFFF		//  Normal read data

#define _CRYHEN_OFF_2L            0xFFBF		//  High speed crystal oscillator disable
#define _CRYHEN_ON_2L             0xFFFF		//  High speed crystal oscillator enable

#define _CRYLEN_OFF_2L            0xFF7F		//  Low speed crystal oscillator disable
#define _CRYLEN_ON_2L             0xFFFF		//  Low speed crystal oscillator enable

#define _FLASH_CP0_ON_2L          0xFFFF       //  flash space 0-1k protect enbale
#define _FLASH_CP0_OFF_2L         0xFEFF       //  flash space 0-1k protect disbale

#define _FLASH_CP1_ON_2L          0xFFFF       //  flash space 1-2k protect enbale
#define _FLASH_CP1_OFF_2L         0xFDFF       //  flash space 1-2k protect disbale

#define _FLASH_CP2_ON_2L          0xFFFF       // flash space 2-3k protect enbale
#define _FLASH_CP2_OFF_2L         0xFBFF       // flash space 2-3k protect disbale

#define _FLASH_CP3_ON_2L          0xFFFF       // flash space 3-4k protect enbale
#define _FLASH_CP3_OFF_2L         0xF7FF       // flash space 3-4k protect disbale

#define _FLASH_CP4_ON_2L          0xFFFF       // flash space 4-5k protect enbale
#define _FLASH_CP4_OFF_2L         0xEFFF       // flash space 4-5k protect disbale

#define _FLASH_CP5_ON_2L          0xFFFF       // flash space 5-6k protect enbale
#define _FLASH_CP5_OFF_2L         0xDFFF       // flash space 5-6k protect disbale

#define _FLASH_CP6_ON_2L          0xFFFF       // flash space 6-7k protect enbale
#define _FLASH_CP6_OFF_2L         0xBFFF       // flash space 6-7k protect disbale

#define _FLASH_CP7_ON_2L          0xFFFF       // flash space 7-8k protect enbale
#define _FLASH_CP7_OFF_2L         0x7FFF       // flash space 7-8k protect disbale

//;----- CONFIG2 Options --------------------------------------------------------
#define _TWDT_111_3L              0xFFFF	   //	WDT overflow time 8.32s
#define _TWDT_110_3L              0xFFFE	   //	WDT overflow time 4.224s
#define _TWDT_101_3L              0xFFFD	   //	WDT overflow time 2.176s
#define _TWDT_100_3L              0xFFFC	   //	WDT overflow time 1.152s
#define _TWDT_011_3L              0xFFFB	   //	WDT overflow time 640ms
#define _TWDT_010_3L              0xFFFA	   //	WDT overflow time 384ms
#define _TWDT_001_3L              0xFFF9	   //	WDT overflow time 256ms
#define _TWDT_000_3L              0xFFF8	   //	WDT overflow time 128ms

#define _WDTEN_OFF_3L             0xFFF7       //  WDT disabled
#define _WDTEN_ON_3L              0xFFFF       //  WDT enabled

#define _FCPU_4T_3L               0xFFFF       //  4 Instruction cycle
#define _FCPU_2T_3L               0xFFEF       //  2 Instruction cycle

#define _PSUT_8_3L                0xFFFF       //  Power on delay  19.52ms
#define _PSUT_4_3L                0xFFDF       //  Power on delay  292.48ms
#define _PSUT_2_3L                0xFFBF       //  Power on delay  873.25ms
#define _PSUT_1_3L                0xFF9F       //  Power on delay  1.87ms

#define _DBG_ON_3L                0xFFFF       //  DEBUG mode  ENABLE
#define _DBG_OFF_3L               0xFF7F       //  DEBUG mode  DISABLE

//;----- CONFIG3 Options --------------------------------------------------------
#define _DBGS_IOSEL_1_4L          0xFFFF     // DEBUG IO Select PA0 and PA2
#define _DBGS_IOSEL_0_4L          0xFFFE     // DEBUG IO Select PA5 and PC2

#define _IESO_OFF_4L              0xFFFD     // Disable dual speed start mode
#define _IESO_ON_4L               0xFFFF     // Enable  dual speed start mode

#define _FCMEN_ON_4L              0xFFFF     // Disable system clock failure monitoring
#define _FCMEN_OFF_4L             0xFFFB     // Enable system clock failure monitoring

#define _FLDIS_ON_4L              0xFFFF     // Read FLASH control enable in SWD mode
#define _FLDIS_OFF_4L             0xFFF7     // Read FLASH control disable in SWD mode

#define _EEDIS_ON_4L              0xFFFF     // Read EEPROM control enable in SWD mode
#define _EEDIS_OFF_4L             0xFFEF     // Read EEPROM control disable in SWD mode

#define _ENVDDL_ON_4L             0xFFFF     // Low voltage read enable bit of FLASH
#define _ENVDDL_OFF_4L            0xFFDF     // Low voltage read disable bit of FLASH

#define _OSCM_HIRC_16M_4L         0xFFFF     // HIRC(32MHZ) AS MAIN CLOCK
#define _OSCM_LIRC_1M_4L          0xFFBF     // LIRC(1MHZ) AS MAIN CLOCK
#define _OSCM_EHRC_16M_4L         0xFF7F     // CRYSTALL HIGH(32MHZ) AS MAIN CLOCK
#define _OSCM_LIRC_32K_4L         0xFF3F     // LIRC(32KHZ) AS MAIN CLOCK

/* Initialise device EEPROM (if available) with 8 bytes of data at a time eg.
 * // store initial values to first 16-bytes of EEPROM address range.
 * __EEPROM_DATA(0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07);
 * __EEPROM_DATA(0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F);*/
#if _EEPROMSIZE > 0
 #define __EEPROM_DATA(a, b, c, d, e, f, g, h) \
			 asm("\tpsect eeprom_data,class=EEDATA"); \
			 asm("\tdb\t" ___mkstr(a) "," ___mkstr(b) "," ___mkstr(c) "," ___mkstr(d) "," \
				      ___mkstr(e) "," ___mkstr(f) "," ___mkstr(g) "," ___mkstr(h))
#else
 #define __EEPROM_DATA(a, b, c, d, e, f, g, h)	// Added only for code portability
#endif

// Various helper macros used in EEPROM/flash routines
#if	_EEPROMSIZE > 256
 #define _LOAD_EEADR(addr)	(EEADRH=(((addr)>>8)&0xFF),EEADR=((addr)&0xFF))
#else
 #define _LOAD_EEADR(addr)	(EEADR=((addr)&0xFF))
#endif

#if	_EEPROMSIZE > 0
 #define _CLEAR_EEIF()	EEIF=0
#else
 #define _CLEAR_EEIF()
#endif

#if defined(SMALL_DATA)
 #define _LOAD_TBLPTR(addr)	TBLPTRU=0;TBLPTR=(far unsigned char*)(addr)
#else
 #define _LOAD_TBLPTR(addr)	TBLPTR=(far unsigned char*)(addr)
#endif

#if(_EEPROMSIZE == 0)
 #define EEPROM_READ(addr)	0	// Added only for code portability
#elif	(_ERRATA_TYPES & ERRATA_EEDATARD)
	/* For chips which must read EEDATA immediately after RD is
	 * set, EEDATA is read into temp variable EEADR because, if
	 * the result of EEPROM_READ is returned to an indirect
	 * object, it may take several instructions to set up access
	 * to that object. */
 #define EEPROM_READ(addr)   \
	 (_LOAD_EEADR(addr),\
	 CARRY=GIE,GIE=0,   \
	 EECON1&=0x3F,RD=1, \
	 EEADR=EEDATA,	    \
	 GIE=CARRY,	    \
	 (EEADR))
#else 	/* Plain and simple version */
 #define EEPROM_READ(addr)    \
	 (_LOAD_EEADR(addr),  \
	 EECON1&=0x3F,RD=1,   \
	 (EEDATA))
#endif

#if(_EEPROMSIZE == 0)
 #define EEPROM_WRITE(addr, value)	// Added only for code portability
#else
 #define EEPROM_WRITE(addr, value)			\
	do{						\
		while(WR)continue;			\
		_LOAD_EEADR(addr);			\
		EEDATA=(value);				\
		EECON1&=0x3F;				\
		CARRY=0;if(GIE)CARRY=1;GIE=0;		\
		WREN=1;EECON2=0x55;EECON2=0xAA;WR=1;	\
		_CLEAR_EEIF();WREN=0;			\
		if(CARRY)GIE=1;				\
	}while(0)
#endif



#endif
